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公开(公告)号:EP3251306A1
公开(公告)日:2017-12-06
申请号:EP16706065.6
申请日:2016-01-29
申请人: Nicira Inc.
IPC分类号: H04L12/713 , H04L12/715 , H04L12/24 , H04L12/703
摘要: A novel design of a gateway that handles traffic in and out of a network by using a datapath pipeline is provided. The datapath pipeline includes multiple stages for performing various data-plane packet-processing operations at the edge of the network. The processing stages include centralized routing stages and distributed routing stages. The processing stages can include service-providing stages such as NAT and firewall. The gateway caches the result previous packet operations and reapplies the result to subsequent packets that meet certain criteria. For packets that do not have applicable or valid result from previous packet processing operations, the gateway datapath daemon executes the pipelined packet processing stages and records a set of data from each stage of the pipeline and synthesizes those data into a cache entry for subsequent packets.
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公开(公告)号:EP3716553A1
公开(公告)日:2020-09-30
申请号:EP20175769.7
申请日:2016-06-27
申请人: Nicira, Inc.
发明人: AGARWAL, Vivek , CHANDRASHEKHAR, Ganesan , SUBRAMANIYAM, Rahul, Korivi , WANG, Howard , SINGH, Ram, Dular
IPC分类号: H04L12/931 , H04L12/46 , H04L12/721 , H04L12/771 , H04L12/713 , G06F9/455
摘要: A LRE (logical routing element) that have LIFs that are active in all host machines spanned by the LRE as well as LIFs that are active in only a subset of those spanned host machines is provided. A host machine having an active LIF for a particular L2 segment would perform the L3 routing operations for network traffic related to that L2 segment. A host machine having an inactive LIF for the particular L2 segment would not perform L3 routing operations for the network traffic of the L2 segment.
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公开(公告)号:EP3669504A1
公开(公告)日:2020-06-24
申请号:EP18830019.8
申请日:2018-10-23
申请人: Nicira, Inc.
IPC分类号: H04L12/713 , H04L12/931 , H04L29/08 , H04L12/24 , H04L29/12 , H04L12/707 , H04L12/703 , H04L12/741 , H04L12/715 , H04L12/717
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公开(公告)号:EP3571822A1
公开(公告)日:2019-11-27
申请号:EP18706345.8
申请日:2018-02-02
申请人: Nicira Inc.
发明人: CHOPRA, Amit , LI, Chen , CHANDRASHEKHAR, Ganesan , YANG, Jinqiang , PILLAI, Sanal , QIAN, Bin
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公开(公告)号:EP3566402A1
公开(公告)日:2019-11-13
申请号:EP18702040.9
申请日:2018-01-12
申请人: Nicira, Inc.
发明人: JAIN, Jayant , CHANDRASHEKHAR, Ganesan , SENGUPTA, Anirban , THAKKAR, Pankaj , TESSMER, Alexander
IPC分类号: H04L12/721 , H04L12/715 , H04L12/931 , H04L12/46
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16.
公开(公告)号:EP3411790A1
公开(公告)日:2018-12-12
申请号:EP17703007.9
申请日:2017-01-18
申请人: Nicira Inc.
发明人: LAMBETH, W. Andrew , STABILE, James Joseph , CHANDRASHEKHAR, Ganesan , THAKKAR, Pankaj , BALLAND, Peter J. III , GANICHEV, Igor
IPC分类号: G06F9/50 , H04L12/931 , G06F9/44
CPC分类号: G06F9/5077 , G06F8/71
摘要: Some embodiments provide a method for determining a realization status of one or more logical entities of a logical network. The method, each time a particular event occurs, increments the value of a realization number and publishes the incremented value to a set of controllers of the logical network. Upon receiving data that specifies the state of a logical entity of the logical network, the method publishes the logical entity state's data to the set of controllers. In some embodiments, the method queries the set of controllers for a realization status of the state data for a set of logical entities that is published to the set of controllers up to a particular point of time. The submitted query, in some embodiments, includes a particular value of the realization number associated with the particular point of time.
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公开(公告)号:EP3031178A2
公开(公告)日:2016-06-15
申请号:EP14796935.6
申请日:2014-10-10
申请人: Nicira Inc.
发明人: CHANDRASHEKHAR, Ganesan , SUBRAMANIYAM, Rahul, Korivi , SINGH, Ram, Dular , AGARWAL, Vivek , WANG, Howard
IPC分类号: H04L12/713
CPC分类号: H04L45/586
摘要: Some embodiments provide a system that includes several host machines for hosting several virtual machines and a physical network for interconnecting the host machines. Each host machine includes a managed physical switching element (MPSE) including several ports for performing link layer forwarding of packets to and from a set of virtual machines running on the host machine. Each port is associated with a unique media access control (MAC) address. Each host machine includes a managed routing element (MPRE) for receiving a data packet from a port of the MPSE and performing network layer routing in order to forward the received data packet from a first virtual machine of a first network segment to a second virtual machine of a second network segment.
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公开(公告)号:EP4164196A1
公开(公告)日:2023-04-12
申请号:EP22209709.9
申请日:2018-10-23
申请人: Nicira, Inc.
IPC分类号: H04L45/00
摘要: A method for a network controller that manages a logical network spanning multiple physical locations. For each physical location hosting data compute nodes (DCNs) belonging to the logical network, the method defines a centralized routing component for processing data messages between the DCNs hosted at the physical location and networks external to the logical network, assigns an active instance of the centralized routing component to operate at the physical location, and assigns a standby instance of the centralized routing component to operate at one of the other physical locations.
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19.
公开(公告)号:EP3677009A1
公开(公告)日:2020-07-08
申请号:EP19704538.8
申请日:2019-01-25
申请人: Nicira Inc.
发明人: HIRA, Mukesh , JAIN, Jayant , CHANDRASHEKHAR, Ganesan , SENGUPTA, Anirban , THAKKAR, Pankaj , TESSMER, Alexander , AGARWAL, Vivek
IPC分类号: H04L29/06 , H04L12/931 , G06F21/53
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公开(公告)号:EP3629529A1
公开(公告)日:2020-04-01
申请号:EP19209363.1
申请日:2014-12-30
申请人: Nicira Inc.
发明人: AGARWAL, Vivek , CHANDRASHEKHAR, Ganesan , SUBRAMANIYAM, Rahul Korivi , SINGH, Ram Dular , WANG, Howard
IPC分类号: H04L12/707 , H04L12/713 , H04L12/931
摘要: A logical routing element (LRE) having multiple designated instances for routing packets from physical hosts (PH) to a logical network is provided. A PH in a network segment with multiple designated instances can choose among the multiple designated instances for sending network traffic to other network nodes in the logical network according to a load balancing algorithm. Each logical interface (LIF) of an LRE is defined to be addressable by multiple identifiers or addresses, and each LIF identifier or address is assigned to a different designated instance.
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