DISTRIBUTED LOGICAL L3 ROUTING
    2.
    发明公开

    公开(公告)号:EP3605969A1

    公开(公告)日:2020-02-05

    申请号:EP19199021.7

    申请日:2012-08-17

    申请人: Nicira Inc.

    IPC分类号: H04L12/715

    摘要: A method for logically routing a packet between a source machine that is in a first logical domain and a destination machine that is in a second logical domain is described. The method configures a managed switching element as a second-level managed switching element. The method configures a router in a host that includes the second-level managed switching element. The method communicatively couples the second-level managed switching element with the router. The method causes the router to route a packet when the router receives a packet from the first logical domain that is addressed to the second logical domain.

    ASYMMETRIC CONNECTION WITH EXTERNAL NETWORKS

    公开(公告)号:EP3471352A1

    公开(公告)日:2019-04-17

    申请号:EP18208713.0

    申请日:2014-09-10

    申请人: Nicira Inc.

    IPC分类号: H04L12/721 H04L12/715

    摘要: A system that allows for the use of direct host return ports (abbreviated "DHR ports") on managed forwarding elements 215, 225 to bypass gateways 250 in managed networks 200. The DHR ports provide a direct connection from certain managed forwarding elements 215, 225 in the managed network 200 to remote destinations 230 that are external to the managed network. Managed networks 200 can include both a logical abstraction layer and physical machine layer. At the logical abstraction layer, the DHR port is treated as a port on certain logical forwarding elements. The DHR port transmits the packet to the routing tables of the physical layer machine 210, 220 that hosts the logical forwarding element without any intervening transmission to other logical forwarding elements. The routing tables of the physical layer machine 210, 220 then strip any logical context associated with a packet and forwarding the packet to the remote destination 230 without any intervening forwarding to a physical gateway provider 250.

    HIERARCHICAL CONTROLLER CLUSTERS FOR INTERCONNECTING DIFFERENT LOGICAL DOMAINS

    公开(公告)号:EP2745473B1

    公开(公告)日:2018-09-19

    申请号:EP12823387.1

    申请日:2012-08-17

    申请人: Nicira, Inc.

    摘要: Some embodiments provide a novel network control system for managing a set of switching elements in a network. The network control system includes a first set of network controllers for managing a first set of switching elements that enable communication between a first set of machines. The network control system includes a second set of network controllers for managing a second set of switching elements that enable communication between a second set of machines. The second set of switching elements is separate from the first set of switching elements and the second set of machines is separate from the first set of machines. The network control system includes a third set of network controllers for managing the first and second sets of network controllers in order to enable communication between machines in the first set of machines and machines in the second set of machines.

    LOGICAL ROUTER WITH MULTIPLE ROUTING COMPONENTS
    10.
    发明公开
    LOGICAL ROUTER WITH MULTIPLE ROUTING COMPONENTS 审中-公开
    具有多个路由组件的逻辑路由器

    公开(公告)号:EP3251306A1

    公开(公告)日:2017-12-06

    申请号:EP16706065.6

    申请日:2016-01-29

    申请人: Nicira Inc.

    摘要: A novel design of a gateway that handles traffic in and out of a network by using a datapath pipeline is provided. The datapath pipeline includes multiple stages for performing various data-plane packet-processing operations at the edge of the network. The processing stages include centralized routing stages and distributed routing stages. The processing stages can include service-providing stages such as NAT and firewall. The gateway caches the result previous packet operations and reapplies the result to subsequent packets that meet certain criteria. For packets that do not have applicable or valid result from previous packet processing operations, the gateway datapath daemon executes the pipelined packet processing stages and records a set of data from each stage of the pipeline and synthesizes those data into a cache entry for subsequent packets.