摘要:
An array substrate (400) comprising a first pixel electrode (491a) overlapped with first and second power lines (431, 435) extended along a gate line (421), the first and second power lines (431, 435) being adapted to receive voltages having different polarities, respectively, the first pixel electrode (491a) being electrically connected to a first data line (471a; Dj); a second pixel electrode (491b) overlapped with the first and second power lines (431, 435), the second pixel electrode (491b; 591b) being electrically connected to a second data line (471b; Dj+1) being adapted to receive a voltage having an opposite polarity to a voltage applied to the first data line (471a; Dj); a first common electrode (491c) overlapping with the first and second power lines (431; 435), the first common electrode (491c) being electrically connected to the first power line (431); and a second common electrode (491d) overlapping with the first and second power lines (431; 435), the second common electrode (491d) being electrically connected to the second power line (435); wherein a capacitance (Cst) of the first common electrode (491c) with the second power line (435) is substantially the same as the sum of the capacitances of a capacitor (Csg) formed by overlapping the first pixel electrode (491a) and the first power line (431) and a capacitor (Csa) formed by overlapping the first pixel electrode (491a) and the second power line (435), and a capacitance (Cst) of the second common electrode (491d) with the first power line (431) is substantially the same as the sum of the capacitances of a capacitor (Csg) formed by overlapping the second pixel electrode (491b) and the first power line (431) and a capacitor (Csa) formed by overlapping the second pixel electrode(491b) and the second power line (435).
摘要:
A liquid crystal display includes: first and second gate lines disposed on the first substrate and which respectively transmit first and second gate signals; first, second and third data lines disposed on the first substrate; a first switching element connected to the first gate line and the first data line; a second switching element connected to the first gate line and the second data line; a third switching element connected to the second gate line and the second data line; a fourth switching element connected to the second gate line and the third data line; first and second pixel electrodes respectively connected to the first and second switching and which form a first liquid crystal capacitor; and third and fourth pixel electrodes respectively connected to the third and fourth switching elements and which form a second liquid crystal capacitor.
摘要:
In an array substrate (100) and a method of manufacturing the array substrate (100), an array substrate (100) includes a first switching element (Qa), a second switching element (Qb), a third switching element (Qc) and a fourth switching element (Qd). The first switching element (Qa) is electrically connected to a first data line (171a). The second switching element (Qb) is electrically connected to a second data line (171b) adjacent to the first data line (171a). The third switching element (Qc) is electrically connected to a data power line (171c) interposed between the first and second data lines (171a,171b). The fourth switching element (Qd) is electrically connected to a gate power line (125) receiving a voltage having different polarity from a voltage applied to the data power line (171c). Therefore, light transmittance, opening ratio and display quality are improved.
摘要:
In an array substrate (100) and a method of manufacturing the array substrate (100), an array substrate (100) includes a first switching element (Qa), a second switching element (Qb), a third switching element (Qc) and a fourth switching element (Qd). The first switching element (Qa) is electrically connected to a first data line (171a). The second switching element (Qb) is electrically connected to a second data line (171b) adjacent to the first data line (171a). The third switching element (Qc) is electrically connected to a data power line (171c) interposed between the first and second data lines (171a,171b). The fourth switching element (Qd) is electrically connected to a gate power line (125) receiving a voltage having different polarity from a voltage applied to the data power line (171c). Therefore, light transmittance, opening ratio and display quality are improved.