CHANNEL MAPPING IN A WIRELESS COMMUNICATION SYSTEM
    12.
    发明授权
    CHANNEL MAPPING IN A WIRELESS COMMUNICATION SYSTEM 有权
    信道分配在无线通信系统

    公开(公告)号:EP1495569B1

    公开(公告)日:2007-11-28

    申请号:EP03717442.2

    申请日:2003-04-08

    申请人: IPWireless, Inc.

    发明人: BEALE, Martin

    IPC分类号: H04L1/00

    摘要: An arrangement and method for channel mapping in a UTRA TDD HSDPA wireless communication system by applying interleaving functions in first (530) and second (540) interleaving means to a bit sequence to produce symbols for mapping to physical channels, the first and second interleaving means being arranged to map symbols from respectively systematic and parity bits in a predetermined scheme, e.g., mapping symbols in a forward direction when a channel has an even index number, and in a reverse direction when a channel has an odd index number. The symbols may comprise bit-pairs, each of a systematic bit and parity bit. Systematic bits are preferably mapped to high reliability bit positions in TDD HSDPA, achieving a performance gain of between 0.2dB and 0.5dB. The forwards/reverse mapping allows a degree of interleaving that improves system performance in fading channels or channels disturbed by short time period noise or interference.

    INCREASING CAPACITY IN WIRELESS COMMUNICATIONS

    公开(公告)号:EP2505017B1

    公开(公告)日:2018-10-31

    申请号:EP09851582.8

    申请日:2009-11-27

    IPC分类号: H04W28/00 H04L1/18

    摘要: Techniques to increase the capacity of a W-CDMA wireless communications system. In an exemplary embodiment, early termination (400) of one or more transport channels on a W-CDMA wireless communications link is provided. In particular, early decoding (421, 423) is performed on slots as they are received over the air, and techniques are described for signaling (431, 432) acknowledgment messages (ACK's) for one or more transport channels correctly decoded to terminate the transmission of those transport channels. The techniques may be applied to the transmission of voice signals using the adaptive multi-rate (AMR) codec. Further exemplary embodiments describe aspects to reduce the transmission power and rate of power control commands sent over the air, as well as aspects for applying tail-biting convolutional codes (1015) in the system.

    EXTENDED TURBO INTERLEAVERS FOR PARALLEL TURBO DECODING
    16.
    发明公开
    EXTENDED TURBO INTERLEAVERS FOR PARALLEL TURBO DECODING 审中-公开
    EXTENDED TURBO交织器并行turbo解码

    公开(公告)号:EP2399341A4

    公开(公告)日:2014-12-24

    申请号:EP10846398

    申请日:2010-02-18

    申请人: NOKIA CORP

    摘要: A first grouping of memory space addresses is generated for systematic bits of a received codeword; a second grouping of memory space addresses is generated for a first set of coding bits of the received codeword, wherein the first set of coding bits comprises an ascending order; and a third grouping of memory space addresses is generated for a second set of coding bits of the received codeword, wherein the second set of coding bits comprises an interleaved order. A sub-codeword of the received codeword is decoded in parallel by accessing the first set of coding bits using the addresses in the second grouping of memory spaces. In turn, another sub-codeword of the received codeword is decoded in parallel by accessing the second set of coding bits using the addresses in the third grouping of memory spaces. Apparatus and a memory storing a computer program are also detailed.

    EXTENDED TURBO INTERLEAVERS FOR PARALLEL TURBO DECODING
    18.
    发明公开
    EXTENDED TURBO INTERLEAVERS FOR PARALLEL TURBO DECODING 审中-公开
    EXTENDED TURBO交织器并行turbo解码

    公开(公告)号:EP2399341A1

    公开(公告)日:2011-12-28

    申请号:EP10846398.5

    申请日:2010-02-18

    申请人: Nokia Corporation

    摘要: A first grouping of memory space addresses is generated for systematic bits of a received codeword; a second grouping of memory space addresses is generated for a first set of coding bits of the received codeword, wherein the first set of coding bits comprises an ascending order; and a third grouping of memory space addresses is generated for a second set of coding bits of the received codeword, wherein the second set of coding bits comprises an interleaved order. A sub- codeword of the received codeword is decoded in parallel by accessing the first set of coding bits using the addresses in the second grouping of memory spaces. In turn, another sub-codeword of the received codeword is decoded in parallel by accessing the second set of coding bits using the addresses in the third grouping of memory spaces. Apparatus and a memory storing a computer program are also detailed.