公开(公告)号：EP1387486B1

公开(公告)日：2008-08-06

申请号：EP03014428.1

申请日：1997-02-21

申请人： FUJITSU LIMITED

发明人： Kawai, Takahisa ,  Okamoto, Itsuo

IPC分类号： H03G1/00 ,  H03F3/193

CPC分类号： H03F3/1935 ,  H03F1/306 ,  H03F3/24 ,  H03F2200/15 ,  H03F2200/18 ,  H03F2200/211 ,  H03F2200/405 ,  H03F2200/54 ,  H03F2200/75 ,  H03G1/0017 ,  H03G1/0029 ,  H03G1/007

公开(公告)号：EP1639700A1

公开(公告)日：2006-03-29

申请号：EP04741499.0

申请日：2004-04-30

申请人： MOTOROLA, INC.

发明人： BEN-AYUN, Moshe, Motorola Israel Limited ,  BEN-SALMON, Avi, Motorola Israel Limited ,  ROZENTAL, Mark, Motorola Israel Limited

IPC分类号： H03F1/34

CPC分类号： H04L27/36 ,  H03F1/32 ,  H03F1/34 ,  H03F3/24 ,  H03F2200/211 ,  H03F2200/321 ,  H03F2200/336 ,  H03F2200/393

摘要： In accordance with the present invention there is those provided a Cartesian loop transmitter (100) having an isolator eliminator circuitry (106) comprising a set of low pass (138, 142) and band pass (140, 144) filters for each of an I- and Q-channels, root mean square detectors (146, 148) and a divider (150) connected to a comparator (152) are received by a microporcessor (154) which controls attenuation setting. There is also provided a method of adjusting an output level of such transmitter (100). Said method comprises the step of measuring an on-channel signal level (206) and a noise level (208) and then calculating a ratio of said noise to said on-channel signal (214). If the ratio exceeds a defined threshold (216) an attenuation of the input attenuators is increased (218).

摘要翻译： 根据本发明，提供了一种具有隔离器消除器电路（106）的笛卡尔环路发送器（100），所述隔离器消除器电路包括用于I中的每一个的一组低通（138,142）和带通（140,144） - 和Q通道，连接到比较器（152）的均方根检测器（146,148）和分频器（150）由控制衰减设置的微处理器（154）接收。 还提供了一种调节这种发射机（100）的输出电平的方法。 所述方法包括测量信道上信号电平（206）和噪声电平（208）然后计算所述噪声与所述信道上信号（214）的比率的步骤。 如果该比率超过定义的阈值（216），则输入衰减器的衰减增加（218）。

公开(公告)号：EP1618653A1

公开(公告)日：2006-01-25

申请号：EP04759822.2

申请日：2004-04-09

申请人： RAYTHEON COMPANY

发明人： ADLERSTEIN, Michael, G. ,  TREMBLAY, John, C.

IPC分类号： H03F3/60 ,  H03F1/52

CPC分类号： H03G11/04 ,  H03F1/523 ,  H03F3/601 ,  H03F2200/211 ,  H03F2200/258

摘要： A limiter circuit includes a rectification circuit coupled to an input of the limiter circuit. The rectification circuit produces a voltage having a predetermined average level. The level is a function of an input signal fed to the input of the limiter circuit. A voltage divider circuit is coupled to the rectification circuit for producing an output voltage having a level proportional to the input signal. An enhancement mode field effect transistor has a gate electrode fed by the output voltage produced by the voltage divider circuit. The transistor has drain and source electrodes coupled to an output of the limiter circuit and a reference potential, respectively. A transmission line is coupled between the input of the limiter and the output of the limiter circuit. The transmission line has an electrical length nlambda/4, where lambda is the nominal operating wavelength of the limiter circuit and n is an odd integer. The use of an enhancement mode transistor with a positive gate threshold for conduction, greatly simplifies the limiter circuit compared with conventional designs using depletion mode transistors.

公开(公告)号：EP1387486A3

公开(公告)日：2005-11-23

申请号：EP03014428.1

申请日：1997-02-21

申请人： FUJITSU LIMITED

发明人： Kawai, Takahisa ,  Okamoto, Itsuo

IPC分类号： H03G1/00 ,  H03F3/193

CPC分类号： H03F3/1935 ,  H03F1/306 ,  H03F3/24 ,  H03F2200/15 ,  H03F2200/18 ,  H03F2200/211 ,  H03F2200/405 ,  H03F2200/54 ,  H03F2200/75 ,  H03G1/0017 ,  H03G1/0029 ,  H03G1/007

摘要： An amplifier circuit includes a first FET (95) of an enhancement type having a gate supplied with an input signal (IN) and a gate bias voltage (VGBS), and a drain via which an amplified output signal (OUT) is output, a current path directed to a source from the gate being formed; a second FET (100) of the enhancement type having a drain connected to a gate bias supply source for the first FET, a gate supplied with a control signal (V contro14 ), and a source via which a source voltage controlled by the control signal is output, the source voltage being supplied to the gate of the first FET (95) as the gate bias voltage; and a resistance element (102) having a first end connected to the source of the second FET (100) and the gate of the first FET (95), and a second end grounded.

公开(公告)号：EP1387486A2

公开(公告)日：2004-02-04

申请号：EP03014428.1

申请日：1997-02-21

申请人： FUJITSU LIMITED

发明人： Kawai, Takahisa ,  Okamoto, Itsuo

IPC分类号： H03G1/00 ,  H03F3/193

CPC分类号： H03F3/1935 ,  H03F1/306 ,  H03F3/24 ,  H03F2200/15 ,  H03F2200/18 ,  H03F2200/211 ,  H03F2200/405 ,  H03F2200/54 ,  H03F2200/75 ,  H03G1/0017 ,  H03G1/0029 ,  H03G1/007

摘要： An amplifier circuit includes a first FET (95) of an enhancement type having a gate supplied with an input signal (IN) and a gate bias voltage (VGBS), and a drain via which an amplified output signal (OUT) is output, a current path directed to a source from the gate being formed; a second FET (100) of the enhancement type having a drain connected to a gate bias supply source for the first FET, a gate supplied with a control signal (V contro14 ), and a source via which a source voltage controlled by the control signal is output, the source voltage being supplied to the gate of the first FET (95) as the gate bias voltage; and a resistance element (102) having a first end connected to the source of the second FET (100) and the gate of the first FET (95), and a second end grounded.

摘要翻译： 放大器电路包括具有提供有输入信号（IN）的栅极和栅极偏置电压（VGBS）的增强型的第一FET（95）和输出放大的输出信号（OUT）的漏极， 从正在形成的栅极引导到源极的电流通路; 增强型的第二FET（100）具有连接到用于第一FET的栅极偏置电源的漏极，提供有控制信号（Vcontro14）的栅极和由控制信号控制的源极电压的源极 输出，将源极电压作为栅极偏置电压提供给第一FET（95）的栅极; 和电阻元件（102），其第一端连接到第二FET（100）的源极和第一FET（95）的栅极，第二端接地。