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公开(公告)号:EP1647977B1
公开(公告)日:2013-01-16
申请号:EP05017385.5
申请日:1999-01-21
Applicant: YAMAHA CORPORATION
Inventor: Nakajo, Yukihisa
IPC: G11B7/0045 , G11B7/126 , G11B7/00
CPC classification number: G11B7/00456 , G11B7/006 , G11B7/126
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公开(公告)号:EP1615215A3
公开(公告)日:2012-08-08
申请号:EP05019025.5
申请日:2000-05-22
Applicant: Pioneer Corporation
Inventor: Kuroda, Kazuo
CPC classification number: G11B7/00736 , G11B7/0045 , G11B7/007 , G11B7/126 , G11B7/24082 , G11B7/261 , G11B7/263 , G11B19/04 , G11B20/00086 , G11B20/0021 , G11B20/00253 , G11B20/00326 , G11B20/00586 , G11B20/0092 , G11B20/1217 , G11B20/1833 , G11B2020/1259 , G11B2020/1285
Abstract: On an information record medium (10, 11), record information can be recorded one time or a plurality of times by a predetermined record format. An apparatus for manufacturing the information record medium by using a stamper (27, 28) is provided with an embossed pit array forming device (20 to 26, 50) for forming on the stamper as an embossed pit array, pre-record data (SFi) which is a predetermined data row to disable overwriting on the record information in a pre-record area, which is set in advance in a range including an area (13c) assigned to information required to control a reproduction of the record information, which is recorded by the predetermined record format.
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公开(公告)号:EP1496503A4
公开(公告)日:2008-05-14
申请号:EP03746420
申请日:2003-04-03
Applicant: TDK CORP
Inventor: SHIBUYA GIICHI
CPC classification number: G11B7/126 , H01S5/02212 , H01S5/02296 , H01S5/0427 , H01S5/0683
Abstract: A semiconductor laser driving circuit has a driving IC (4) and a substrate on which the driving IC is formed. The IC has a switching element that generates a driving signal; high and low potential supply terminals (42,43) for supplying a power voltage to the switching element; and a driving signal output terminal (44) for externally outputting the driving signal generated by the switching element. The terminals (42-44) are provided side by side on an edge of the body (4a) of the IC. Chip capacitors (51,52) are also provided beside that IC edge and have their respective one ends connected to the high potential supply terminal and the other ends connected to the low potential supply terminal.
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