Systems and methods for multi-level encoding and decoding

    公开(公告)号:EP2843662B1

    公开(公告)日:2018-10-03

    申请号:EP14173906.0

    申请日:2014-06-25

    申请人: LSI Corporation

    IPC分类号: G11B20/18

    摘要: A storage system includes a storage medium operable to maintain a data set, a read/write head assembly operable to write the data set to the storage medium and to read the data set from the storage medium, a multi-level encoder operable to encode the data set at a plurality of different code rates before it is written to the storage medium, and a multi-level decoder operable to decode the data set retrieved from the storage medium and to apply decoded values encoded at a lower code rate when decoding values encoded at a higher code rate.

    SIGNAL QUALITY EVALUATION DEVICE, SIGNAL QUALITY EVALUATION METHOD, AND PLAYBACK DEVICE
    4.
    发明公开
    SIGNAL QUALITY EVALUATION DEVICE, SIGNAL QUALITY EVALUATION METHOD, AND PLAYBACK DEVICE 有权
    设备信号质量评价方法的信号质量评估和播放设备

    公开(公告)号:EP2858070A4

    公开(公告)日:2016-06-15

    申请号:EP13799823

    申请日:2013-04-26

    申请人: SONY CORP

    发明人: SHIRAISHI JUNYA

    摘要: Provided is a signal quality evaluation apparatus, including an error pattern detection unit to which binarized data obtained by performing a PRML decoding process on a reproduced signal of bit information by partial response equalization and maximum likelihood decoding is input, the error pattern detection unit configured to detect at least one specific error pattern that is a bit pattern that is longer than a constraint length of the PRML decoding process, a metric difference calculation unit configured to calculate a metric difference of the at least one specific error pattern that has been detected by the error pattern detection unit, and an index value generation unit configured to generate an index value of a reproduced signal quality by using a distribution of the metric difference obtained by the metric difference calculation unit.

    DECODING DEVICE AND DECODING METHOD
    8.
    发明公开
    DECODING DEVICE AND DECODING METHOD 审中-公开
    VORRICHTUNG UND VERFAHREN ZUM DEKODIEREN

    公开(公告)号:EP2744113A1

    公开(公告)日:2014-06-18

    申请号:EP12821855.9

    申请日:2012-08-01

    IPC分类号: H03M13/19 G11B20/18

    摘要: A control device (211) inputs reliability information on the same data block a plurality of times into a reliability storage memory (202). A reliability generating device (201) generates anew reliability information by performing computation processing based on a stochastic computation by using reliability information generated in the previous cycle that has been saved in the reliability storage memory (202) and reliability information generated in the present cycle, and saves the reliability information generated anew in the reliability storage memory (202) when the decoding is performed by using reliability information on the data block same as that in the previous cycle. A column processing computation device (204) computes a column processing output value by using the reliability information generated anew and saved in the reliability storage memory (202) and a row processing output value.

    摘要翻译: 控制装置(211)将相同数据块上的可靠性信息多次输入到可靠性存储存储器(202)中。 可靠性生成装置(201)通过使用保存在可靠性存储器(202)中的上一个循环中生成的可靠性信息和在本周期中生成的可靠性信息,通过进行基于随机运算的计算处理,生成新的可靠性信息, 并且当通过使用与前一个周期相同的数据块的可靠性信息来执行解码时,将可靠性信息重新生成在可靠性存储存储器(202)中。 列处理计算装置(204)通过使用重新生成并保存在可靠性存储存储器(202)中的可靠性信息和行处理输出值来计算列处理输出值。

    Coding method, coding apparatus, decoding method, and decoding apparatus
    9.
    发明公开
    Coding method, coding apparatus, decoding method, and decoding apparatus 有权
    编码,编码,解码和解码

    公开(公告)号:EP2339583A3

    公开(公告)日:2014-01-22

    申请号:EP10189954.0

    申请日:2010-11-04

    申请人: Sony Corporation

    发明人: Noda, Makoto

    IPC分类号: G11B20/18 G11B20/14 H03M13/00

    摘要: Disclosed herein is a coding method including the step of: coding an information sequence in such a manner that upon performing error correction coding after carrying out RLL coding of the information sequence, the maximum number of consecutive 1-bits or 0-bits is α-β or less in an RLL code word over a range from bit p-α to bit p+α-1 of the RLL code word and that a β-bit error correcting code parity sequence is inserted between bit p-1 and bit p of the RLL code word, where α is a number larger than 1 representing the maximum number of consecutive 0-bits or 1-bits in an n-bit RLL code word and where p is a natural number.