公开(公告)号：EP1712027A1

公开(公告)日：2006-10-18

申请号：EP05711377.1

申请日：2005-01-10

申请人： INTEL CORPORATION

发明人： XIA, Bo ,  JACOBSEN, Eric

IPC分类号： H04L1/00

CPC分类号： H04L1/0057 ,  H03M13/036 ,  H03M13/118 ,  H03M13/1194 ,  H03M13/6516 ,  H04L1/0041

摘要： A low density parity check (LDPC) code is used within a wireless apparatus to perform forward error correction (FEC) coding. Encoding comprises the multiplication (42) with a transpose of a porti9on (44) of a parity check matrix followed by differential encoding (46). In at least embodiment of the invention, a (2000, 1600) bit-length LDPC code is used.

公开(公告)号：EP1628401A1

公开(公告)日：2006-02-22

申请号：EP05009389.7

申请日：2005-04-28

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Kyung, Gyu-Bum Samsung Electronics Co., Ltd. ,  Myung, Se-Ho Samsung Electronics Co., Ltd. ,  Yang, Kyeong-Cheol Samsung Electronics Co., Ltd. ,  Yang, Hyun-Koo Samsung Electronics Co., Ltd. ,  Park, Dong-Seek Samsung Electronics Co., Ltd. ,  Kim, Jae-Yoel Samsung Electronics Co., Ltd. ,  Park, Sung-Eun Samsung Electronics Co., Ltd. ,  Choi, Seung-Hoon Samsung Electronics Co., Ltd. ,  Joo, Pan-Yuh Samsung Electronics Co., Ltd. ,  Jeong, Hong-Sil Samsung Electronics Co., Ltd.

IPC分类号： H03M13/11

CPC分类号： H03M13/116 ,  H03M13/1134 ,  H03M13/118 ,  H03M13/1185 ,  H03M13/1188 ,  H03M13/1194 ,  H03M13/6362

摘要： Disclosed is a device and procedure for coding a block low density parity check (LDPC) code having a variable length. The a device and procedure includes receiving an information word; and coding the information word into a block LDPC code according to a first parity check matrix or a second parity check matrix depending on a length to be applied when generating the information word into the block LDPC code.

摘要翻译： 公开了一种用于编码具有可变长度的块低密度奇偶校验（LDPC）码的装置和过程。 一种设备和过程包括接收信息字; 以及根据在将信息字生成到块LDPC码时要应用的长度，根据第一奇偶校验矩阵或第二奇偶校验矩阵将信息字编码为块LDPC码。

公开(公告)号：EP1580896A2

公开(公告)日：2005-09-28

申请号：EP05250979.1

申请日：2005-02-21

申请人： SONY CORPORATION

发明人： Kan, Makiko, c/o Sony Corporation ,  Yokokawa, Takashi, c/o Sony Corporation ,  Miyauchi, Toshiyuki, c/o Sony Corporation ,  Kikuchi, Atsushi, c/o Sony Corporation

IPC分类号： H03M13/03

CPC分类号： H03M13/1194 ,  H03M13/116 ,  H03M13/118 ,  H03M13/1185

摘要： Disclosed is an apparatus for encoding data into linear codes on a ring R, including: as many shift registers as the length of information input thereto, the shift registers having a plurality of memory elements; a shift adding unit for adding values which are cyclically input depending on a check matrix for the linear codes, from the shift registers; a storage unit for storing parity values of the linear codes; and an accumulative adding unit for adding a sum from the shift adding unit and the parity values of the linear codes stored in the storage unit to each other to determine new parity values of the linear codes, and supplying the new parity values to the storage unit.