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公开(公告)号：EP3158676A1
公开(公告)日：2017-04-26
申请号：EP14744035.8
申请日：2014-07-22
CPC分类号： H04L7/0029 , H03L7/235 , H04L7/0062 , H04L7/0335
摘要： A timing recovery apparatus for receivers is disclosed. The apparatus includes a feedback loop with two parallel branches, each branch having an interpolation filter and a phase detector. The feedback loop additionally includes a combiner to combine a signal from each of the branches.
摘要翻译： 公开了一种用于接收机的定时恢复装置。 该设备包括具有两个并行分支的反馈回路，每个分支具有内插滤波器和相位检测器。 反馈回路还包括组合器，用于组合来自每个分支的信号。
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32.发明公开METHOD FOR OPTIMIZING CLOCK RECOVERY PERFORMANCES AT A COHERENT OPTICAL RECEIVER OF AN OPTICAL WDM TRANSMISSION SYSTEM, RECEIVER ASSOCIATED 审中-公开法在合理卒中恢复服务于光WDM传输系统的相干光接收器，使Receiver
公开(公告)号：EP3086502A1
公开(公告)日：2016-10-26
申请号：EP15164397.0
申请日：2015-04-21
申请人： ALCATEL LUCENT
CPC分类号： H04L7/0083 , H04B10/614 , H04B10/616 , H04L7/027 , H04L7/0335
摘要： The invention relates to a method (Mth) for optimizing clock recovery performances at a coherent optical receiver (Rx) of an optical Wavelength Division Multiplexed transmission system, said method (Mth) comprising the following steps:
- Sampling (Smp_Xp°Yp°), at a samples per symbol rate (xSPS), a pair of complex polarization signals (Xp°, Yp°) of a Polarization Division Multiplexed optical signal (Sg) received from a coherent optical transmitter at a symbol rate (SB), so as to obtain a pair of digital complex polarization signals (Xp, Yp)
- Recovering (Rec_OSC) a receiver clock in the pair of digital complex polarization signals (Xp, Yp), using a clock recovery algorithm, at a clock rate equal to the sample per symbol rate (xSPS)
- Calculating (Calc_Pst) a performance estimate (Pst) of said clock receiver recovery
- If said performance estimate (Pst) is below a performance threshold (Thr), then :
• replacing (Prgm_Alg) the clock recovery algorithm with a selected clock recovery algorithm, and
• modifying (Mod_xSPS) the sample per symbol rate (xSPS) in accordance with a range of acceptable samples per symbol rates for the selected clock recovery algorithm
- Reiterating the previous steps until the performance estimate (Pst) reaches the performance threshold (Thr).摘要翻译： 本发明涉及的方法（第M），用于在一个相干光接收器的光学波分复用传输系统的（Rx）的优化时钟恢复性能，所述方法（M th）时，包括以下步骤： - 采样（Smp_Xp°Y p°） 以每个码元速率的样品（的xSP），一对复极化信号的（XP°，Y p°）的偏振复用光信号的（SG）从相干光发射器接收以符号率（SB），以 获得的一对数字复极化信号的（XP，YP） - 恢复（Rec_OSC）在一对数字复极化信号（p，Y p）的接收机时钟，使用时钟恢复算法，在时钟速率等于由样品 符号率（的xSP） - 计算（Calc_Pst）性能估计所述时钟接收机恢复的（PST） - 如果所述性能估计（PST）低于性能阈值（THR），则：€¢替换（Prgm_Alg）时钟恢复算法 与所选择的时钟恢复 RY算法，和€¢改性（Mod_xSPS）在雅舞蹈每个符号速率（xSP运营商）将样品与一系列每个符号速率上可接受的样本选择的时钟恢复算法 - 达平顺评分先前的步骤直到性能估计（PST）的性能 阈值（THR）。
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公开(公告)号：EP2530856A1
公开(公告)日：2012-12-05
申请号：EP12163880.3
申请日：2012-04-12
申请人： FUJITSU LIMITED
发明人： Komaki, Kosuke , Nakashima, Hisao
IPC分类号： H04B10/18 , H04B10/148
CPC分类号： H04B10/25073 , H04B10/2569 , H04B10/6971 , H04L7/0087 , H04L7/0335
摘要： A digital coherent receiver includes a sampling phase detector to detect a phase of a sampled digital signal, and a phase adjustor to adjust the sampling phase of the digital signal based upon the detected phase. The phase detector includes filters to equalize the digital signal with different equalization characteristics; sensitivity monitoring phase detectors, each connected to one of the filters and outputting a phase detection signal representing the phase of the output signal from the associated filter together with a sensitivity monitoring signal representing the sensitivity of the phase detection; sensitivity correction coefficient generators, each generating a sensitivity correction coefficient for correcting the associated phase detection signal using a square sum of the sensitivity monitoring signals; and an adder to add the phase detection signals that have been corrected by the sensitivity correction coefficients, and output a phase signal.
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34.发明授权
公开(公告)号：EP1244245B1
公开(公告)日：2004-11-24
申请号：EP02290390.0
申请日：2002-02-19
申请人： ALCATEL
CPC分类号： H04L1/06 , H04B7/0845 , H04L7/0083 , H04L7/0334 , H04L7/0335
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35.发明公开Recherche de l'instant d'échantillonnage optimal dans un système de transmissions par paquets TDMA 有权在eeem TDMAPaketübertragungssystem中的Abtastzeitpunktes的最佳化
公开(公告)号：EP1094631A1
公开(公告)日：2001-04-25
申请号：EP00203512.9
申请日：2000-10-11
CPC分类号： H04L7/007 , H04L7/0029 , H04L7/0335
摘要： L'invention concerne un système de transmission par paquets TDMA entre des terminaux interactifs (2) et une station de tête (1) via un média de transmission (3). Des perturbations telles que du bruit et des distorsions sur le canal peuvent engendrer des décalages en réception par rapport à la fréquence symbole théoriquement utilisée en émission. Le récepteur doit donc sur-échantillonner le signal reçu pour retrouver l'échantillon optimal correspondant au symbole émis. Pour cela, des moyens de recherche de l'instant d'échantillonnage optimal sont prévus pour déterminer le maximum des amplitudes moyennes de tous les échantillons d'entrée fournis par le sur-échantillonnage. L'invention propose une méthode itérative pour récupérer très rapidement cet instant d'échantillonnage optimal en ne calculant les amplitudes moyennes que pour une partie seulement des échantillons d'entrée.
摘要翻译： 来自多个输入样本的最佳样本由迭代过程确定，该迭代过程基于计算输入样本的缩减集合的平均幅度。 这优选地通过确定近似平均最大振幅样本，然后在先前的近似最大样本和下一个这样的样本之间选择另外的样本来实现。 比较器将该选择的样本的平均幅度与先前的近似最大振幅样本进行比较，以确定新的近似值。 独立权利要求包括：（a）配备过采样装置的数据包的接收机; （b）分组传输系统; （c）和用于确定输入数据的最佳采样时刻的方法。
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公开(公告)号：EP0793365A2
公开(公告)日：1997-09-03
申请号：EP97400376.6
申请日：1997-02-20
CPC分类号： H04N5/4401 , H03L7/0814 , H04L7/0029 , H04L7/0335 , H04L27/22 , H04N5/04
摘要： A timing recovery system for a digital signal receiver receives a signal, representing successive symbols, from a transmitter. The symbols are subject to exhibiting multiple symbol rates. The system derives a sample enable signal from the received input signal and employs a single, fixed frequency oscillator. A source (10) of samples representing the received signal are sampled at a fixed frequency. An interpolator (12) is coupled to the sample source and is responsive to a control signal. The interpolator produces samples taken at times synchronized to the successive symbols from the transmitter. A phase error detector (16) is coupled to the interpolator, detects a phase error between the sample times of the transmitter synchronized samples produced by the interpolator and times of the successive transmitter symbols, and supplies a phase error signal. The phase error signal is coupled to one input terminal of a summer (32) and a source (31) of a nominal delay signal is coupled to the other. A numerically controlled delay (34-46) produces the control signal for the interpolator in response to the signal from the summer. An output signal from the interpolator is filtered by a fixed, non-adaptive pulse-shaping filter (14).
摘要翻译： 用于数字信号接收机的定时恢复系统从发射机接收表示连续符号的信号。 符号可以显示多个符号率。 该系统从接收到的输入信号中导出采样使能信号，并采用单个固定频率振荡器。 以固定频率对表示接收信号的样本的源（10）进行采样。 内插器（12）耦合到采样源并响应于控制信号。 内插器产生在与发射机的连续符号同步的时间采集的采样。 相位误差检测器（16）耦合到内插器，检测由内插器产生的发射机同步采样的采样时间与连续发射机符号的时间之间的相位误差，并提供相位误差信号。 相位误差信号耦合到加法器（32）的一个输入端子，标称延迟信号的源极（31）耦合到另一个。 数字控制延迟（34-46）响应于夏季的信号产生内插器的控制信号。 来自内插器的输出信号被固定的非自适应脉冲整形滤波器（14）滤波。
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公开(公告)号：EP0748118A2
公开(公告)日：1996-12-11
申请号：EP96301867.6
申请日：1996-03-19
IPC分类号： H04N7/12
CPC分类号： H04L7/0029 , H04L1/0054 , H04L1/0057 , H04L1/0065 , H04L1/0068 , H04L7/0334 , H04L7/0335 , H04L27/3872 , H04L2027/0028 , H04L2027/0057 , H04L2027/0067 , H04N21/2383 , H04N21/4382
摘要： A CMOS integrated signal processing system for a sampling receiver includes a timing recovery circuit, wherein an on-chip numerically controlled oscillator is operative at periods T that are initially equal to the nominal baud rate of the signals controls a sinc interpolator receiving samples at the sampling rate. A loop filter is coupled to the sinc interpolator and to the numerically controlled oscillator. The arrangement is capable of handling various symbol rates. The system includes a circuit for carrier recovery, having a second on-chip numerically controlled oscillator, a digital derotation circuit responsive to the second numerically controlled oscillator, accepting an in phase component and a quadrature component of the sampled signals. An adaptive phase error estimation circuit is coupled in a feedback loop.
摘要翻译： 用于采样接收机的CMOS集成信号处理系统包括定时恢复电路，其中片上数控振荡器在周期T处工作，周期T最初等于信号的标称波特率，控制正弦内插器在采样时接收采样 率。 环路滤波器耦合到正弦内插器和数控振荡器。 该装置能够处理各种符号率。 该系统包括用于载波恢复的电路，具有第二片上数控振荡器，响应于第二数控振荡器的数字解旋转电路，接受采样信号的同相分量和正交分量。 自适应相位误差估计电路耦合在反馈回路中。
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公开(公告)号：EP0647376A1
公开(公告)日：1995-04-12
申请号：EP93912554.0
申请日：1993-06-03
发明人： LANKL, Berthold , SEBALD, Georg
CPC分类号： H04L7/0334 , H04L7/0062 , H04L7/0335
摘要： The invention relates to a clock phase detector for synchronous data transmission in the receiver of a data transmission system in which, in order to obtain a clock phase criterion from the received signal, two neighbouring main scanning values per symbol duration T and another intermediate scanning value midway between the two are formed. The pattern-dependent jitter is to be eliminated from such a clock phase detector. This is achieved by the invention by a modification to the Gardner process which eliminates the effects of neighbouring symbol interference on the clock phase criterion and thus reduces natural jitter.
摘要翻译： 本发明涉及一种用于数据传输系统的接收机中的同步数据传输的时钟相位检测器，其中为了从接收信号获得时钟相位标准，每个符号持续时间T两个相邻主扫描值和另一个中间扫描值 两者之间的中途形成。 这种时钟相位检测器将消除与模式有关的抖动。 这通过本发明通过修改加德纳过程来实现，该过程消除了相邻符号干扰对时钟相位标准的影响并因此减少了自然抖动。
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公开(公告)号：EP0118119A2
公开(公告)日：1984-09-12
申请号：EP84102234.6
申请日：1984-03-02
申请人： NEC CORPORATION
发明人： Yoshida, Yasuharu
IPC分类号： H04L7/02
CPC分类号： H04L7/0334 , H04L7/0335
摘要： In a timing synchronizing circuit wherein a timing signal is regenerated from a baseband signal subjected to a bandwidth limitation, there are provided a voltage controlled oscillator (5) whose oscillation frequency varies in accordance with a control signal, an A/D converter (11) which samples and shapes the baseband signal by utilizing the output of the voltage controlled oscillator (5), a decision circuit (10) for deciding the polarity of a differential coefficient of the baseband signal at an optimum sampling point on the basis of an output of the A/D converter (11), and a logic circuit (9) responsive to the output of the decision circuit (10) to apply a logical operation to a decision signal derived from the A/D converter (11) and which decides whether or not the baseband signal shifts from a level corresponding to the optimum sampling point, thereby producing the control signal for the volatge controlled oscillator (5). The regenerated timing signal contains only a negligible amount of jitter components and always maintains an optimum timing without using any phase adjustment (Fig. 2).
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公开(公告)号：EP4393121A1
公开(公告)日：2024-07-03
申请号：EP21851722.5
申请日：2021-12-09
发明人： KING, Brandon Gregory , JARRIEL, Jeffrey David , SUTTON, Daniel Joseph , STOLTENBERG, Matthew James
CPC分类号： H04L27/0014 , H04L2027/006520130101 , H04L2027/006720130101 , H04L7/0079 , H04L7/0335 , H04L7/007
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