摘要:
A signal processing device includes: a phase controller configured to control respective phases of an in-phase signal and an quadrature signal, which are obtained by converting an analog signal into a digital signal when a multi-value phase modulation light is demodulated, by digital signal processing; and a control amount provider configured to provide a control amount to the phase controller based on an output of the phase controller.
摘要:
A method and a system are provided including a clock recovery unit comprising a first phase detector unit; an estimation unit comprising a second phase detector unit; the estimation unit being configured to estimate the gain of the second phase detector unit; wherein the estimation unit and the clock recovery unit are configured to operate in parallel.
摘要:
A symbol timing recovery (STR) error detector (10) includes a complex multiplier (14) and a Gardner-type symbol timing error estimator (12) for operation with carrierless amplitude phase (CAP) signals. Quadrature Ir and Qr signals from the system are input to the complex multiplier, which also receives signals from a numerically controlled oscillator (16) operating at the CAP center frequency. The output of the complex multiplier is provided to the input of the Gardner STR error estimator. An added frequency shift allows the Gardner error estimator to function with CAP signals. The output from the error estimator is provided to a loop filter (110) the output of which is provided to an oscillator (112) which generates the symbol timing information (114) for a symbol sampling network (106).
摘要:
A symbol timing recovery (STR) error detector (10) includes a complex multiplier (14) and a Gardner-type symbol timing error estimator (12) for operation with carrierless amplitude phase (CAP) signals. Quadrature Ir and Qr signals from the system are input to the complex multiplier, which also receives signals from a numerically controlled oscillator (16) operating at the CAP center frequency. The output of the complex multiplier is provided to the input of the Gardner STR error estimator. An added frequency shift allows the Gardner error estimator to function with CAP signals. The output from the error estimator is provided to a loop filter (110) the output of which is provided to an oscillator (112) which generates the symbol timing information (114) for a symbol sampling network (106).
摘要:
A receiver for a transmitted quadrature amplitude modulated (QAM) signal representing successive symbols, and including an in-phase (I) component and a quadrature (Q) component. A timing recovery system includes a source of samples (102) representing the QAM signal produced at a fixed frequency. Processing circuitry for the I component includes a first demodulator (104), coupled to the sample source, for demodulating the I component of the QAM signal to baseband; and a first interpolator (108), responsive to a control signal, for producing I component samples taken at times synchronized to the transmitted symbols. Processing circuitry for the Q component includes a second demodulator (114), also coupled to the sample source, for demodulating the Q component of the QAM signal to baseband; and a second interpolator (118), responsive to a control signal, for producing Q component samples taken at times synchronized to the transmitted symbols. A phase error detector (126) detects the phase error between the sample times of the I and Q component samples from the first and second interpolators and times of the successive transmitter symbols. A summer (130) is coupled to the phase error detector and a source of a nominal delay signal. A numerically controlled delay circuit (132), is coupled to the summer, for producing the respective control signals for the first and second interpolators.
摘要:
A CMOS integrated signal processing system for a sampling receiver includes a timing recovery circuit, wherein an on-chip numerically controlled oscillator is operative at periods T that are initially equal to the nominal baud rate of the signals controls a sinc interpolator receiving samples at the sampling rate. A loop filter is coupled to the sinc interpolator and to the numerically controlled oscillator. The arrangement is capable of handling various symbol rates. The system includes a circuit for carrier recovery, having a second on-chip numerically controlled oscillator, a digital derotation circuit responsive to the second numerically controlled oscillator, accepting an in phase component and a quadrature component of the sampled signals. An adaptive phase error estimation circuit is coupled in a feedback loop.
摘要:
The invention relates to a clock phase detector for synchronous data transmission in the receiver of a data transmission system in which, in order to obtain a clock phase criterion from the received signal, two neighbouring main scanning values per symbol duration T and another intermediate scanning value midway between the two are formed. The pattern-dependent jitter is to be eliminated from such a clock phase detector. This is achieved by the invention by a modification to the Gardner process which eliminates the effects of neighbouring symbol interference on the clock phase criterion and thus reduces natural jitter.
摘要:
The invention relates to an apparatus (100) for synchronizing a sampling signal on a communication signal, the communication signal comprising communication symbols, the sampling signal indicating sampling time instants of the communication signal, the apparatus (100) comprising a sampler (101) being configured to sample the communication signal at the sampling time instants indicated by the sampling signal to obtain a sampled communication signal, a filter (103) being configured to filter the sampled communication signal using a first filtering transfer function to obtain a first filtered sampled communication signal, and to filter the sampled communication signal using a second filtering transfer function to obtain a second filtered sampled communication signal, a phase detector (105) being configured to determine a first phase detection signal upon the basis of the first filtered sampled communication signal, and to determine a second phase detection signal upon the basis of the second filtered sampled communication signal, the first phase detection signal indicating a position of a sampling time instant within a communication symbol of the first filtered sampled communication signal, the second phase detection signal indicating a position of a sampling time instant within a communication symbol of the second filtered sampled communication signal, a determiner (107) being configured to determine a first synchronicity measure upon the basis of the first phase detection signal, and to determine a second synchronicity measure upon the basis of the second phase detection signal, the first synchronicity measure and the second synchronicity measure indicating a synchronicity between the sampling signal and the communication signal, and a selector (109) being configured to select the first filtering transfer function or the second filtering transfer function of the filter (103) for filtering the sampled communication signal upon the basis of the first synchronicity measure and the second synchronicity measure for synchronizing the sampling signal on the communication signal.