Video device and method for synchronising time bases of video devices
    34.
    发明公开
    Video device and method for synchronising time bases of video devices 审中-公开
    Videovorrichtung und -verfahren zur Synchronisierung der Zeitbasen von Videovorrichtungen

    公开(公告)号:EP1450555A1

    公开(公告)日:2004-08-25

    申请号:EP03290401.3

    申请日:2003-02-18

    IPC分类号: H04N5/04 H04N5/073

    摘要: A video system comprises a first video device (1) which transmits a video signal (CVS C ) comprising image information and synchronisation information and a second video device which receives said composite video signal (CVS C ). The second device has a time base (21). For synchronising the two devices

    a) synchronisation information (ΦI C , ΦL C ; ΦI M , ΦL M ) is extracted from the video signal (CVS C ) received by the second video device (2) and from the time base (21) of the second video device (2);
    b) a phase difference (ΔΦI, ΔΦL) between the video signal (CVS C ) received by the second video device (2) and the time base (21) of the second video device (2) is determined based on said extracted synchronisation information (ΦI C , ΦL C ; ΦI M , ΦL M ) ;
    c) control information (ΔΦI) of a first type representative of the amount of said phase difference is transmitted to said first device (1); and
    d) in said first device (1) the phase of the video signal (CVS C ) is switched by a phase angle represented by said first type control information (ΔΦI).

    摘要翻译: 视频系统包括发送包括图像信息和同步信息的视频信号(CVSC)的第一视频设备(1)和接收所述复合视频信号(CVSC)的第二视频设备。 第二设备具有时基(21)。 为了同步两个设备,a)从第二视频设备(2)接收的视频信号(CVSC)和从第二视频设备(2)的时基(21)提取同步信息(PHI IC,PHI LC; PHI IM,PHI LM) 第二视频设备(2); b)基于所述第二视频设备(2)接收的视频信号(CVSC)和第二视频设备(2)的时基(21)之间的相位差(DELTA PHI I,DELTA PHI L) 提取同步信息(PHI IC,PHI LC; PHI IM,PHI LM); c)将表示所述相位差的量的第一类型的控制信息(DELTA PHI I)发送到所述第一设备(1); 和d)在所述第一装置(1)中,视频信号(CVSC)的相位被所述第一类型控制信息(DELTA PHI I)表示的相位角切换。

    Video output apparatus and output video changeover control method
    36.
    发明公开
    Video output apparatus and output video changeover control method 有权
    Bildwiedergabegerätund Verfahren zur Umschaltung von Videosignalen

    公开(公告)号:EP1128357A2

    公开(公告)日:2001-08-29

    申请号:EP01103758.7

    申请日:2001-02-15

    IPC分类号: G09G5/12

    摘要: When a changeover instruction is input to video output changeover control section 108, power control section 112 turns on the power to changeover target video output section 102. Timing change section 111 synchronizes sync signal Y output by changeover target video output section 102 with sync signal X output by changeover source video output section 101. Power control section 112 turns off the power to changeover source video output section 101.

    摘要翻译: 当切换指令输入到视频输出切换控制部分108时,功率控制部分112接通切换目标视频输出部分102的电源。定时改变部分111将转换目标视频输出部分102输出的同步信号Y与同步信号X 由切换源视频输出部分101输出。电源控制部分112关闭切换源视频输出部分101的电源。

    METHOD AND CIRCUIT FOR SYNCHRONIZING PHASE
    37.
    发明公开
    METHOD AND CIRCUIT FOR SYNCHRONIZING PHASE 失效
    VERFAHREN UND VORRICHTUNG ZUR PHASENSYNCHRONISATION

    公开(公告)号:EP0779713A1

    公开(公告)日:1997-06-18

    申请号:EP96910207.8

    申请日:1996-04-19

    申请人: SONY CORPORATION

    IPC分类号: H03L7/06

    摘要: Signal (digital sine wave signals) (Sd) stored in a memory means (3) are read. The phase of input signal (analog sine wave signal) (Sr) supplied to an input terminal is compared with that of signal (Sa) generated by D/A-converting the signals (Sd) (by means of a comparator (2)), the reading address signal of the memory means (3) is controlled based on the phase error signal (a) generated as a result of the comparison by the comparator (2) (by means of an address forming circuit (5)). Thus, the phase of the digital sine wave signals (Sd) supplied to an output terminal (6) is synchronized with that of the analog sine wave signals (Sr) supplied to the input terminal (1). Desired digital signals synchronized with the phase of the input signals can be generated by processing the digital signals with a simple constitution.

    摘要翻译: 读取存储在存储器装置(3)中的信号(数字正弦波信号)(Sd)。 提供给输入端子的输入信号(模拟正弦波信号)(Sr)的相位与通过D / A转换信号(Sd)(借助比较器(2))产生的信号(Sa)进行比较, 基于由比较器(2)(借助于地址形成电路(5))的比较结果产生的相位误差信号(a)来控制存储装置(3)的读取地址信号。 因此,提供给输出端子(6)的数字正弦波信号(Sd)的相位与提供给输入端子(1)的模拟正弦波信号(Sr)的相位同步。 可以通过以简单的结构处理数字信号来产生与输入信号的相位同步的期望的数字信号。

    Superimposing circuit
    38.
    发明公开
    Superimposing circuit 失效
    叠加电路

    公开(公告)号:EP0696876A2

    公开(公告)日:1996-02-14

    申请号:EP95112698.6

    申请日:1995-08-11

    IPC分类号: H04N9/64 H04N5/445

    CPC分类号: H04N9/641 H04N5/073 H04N5/272

    摘要: A superimposing circuit (10̸) includes a PAL ID circuit (50̸) in which phases of an external burst signal and a CDG burst signal are compared with each other. If the phases are not coincident with each other, it is determined that polarities of the burst signals are not coincident with each other, and therefore, the PAL ID circuit (50̸) outputs a PAL ID signal to a color encoder (28). In response to the PAL ID signal, the color encoder (28) stops a changeover of the polarity at every 2H such that the polarities of the both burst signals can be made to be coincident with each other.