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公开(公告)号：EP0896475A2
公开(公告)日：1999-02-10
申请号：EP98202172.7
申请日：1995-02-28
发明人： Wise, Adrian Philip , Sotheran, Martin William , Robbins, William Philip , Finch, Helen Rosemary , Boyd, Kevin James
CPC分类号： G06F13/28 , G06F12/0207 , G06F12/04 , G06F12/0607 , G06F13/1673 , G06F13/1689 , H04N19/13 , H04N19/423 , H04N19/61 , H04N19/91
摘要： In a video decoding and decompression system having an input, an output and a plurality of processing stages between the input and the output defining a pipeline, the improvement comprising :
a token generator responsive to a data stream received via said input for generating an interactive interfacing control token, defining a universal adaptation unit, for data functions among said processing stages, wherein said token is variable in length and is transmitted serially through said processing stages of said pipeline, and wherein said token is altered by a said processing stage ;
a first two wire interface disposed between a preceding member and a succeeding member of a pair of adjacent stages comprising an input data storage device (LDIN) and an output data storage device (LDOUT) in each member of said pair, with an output data storage device of the preceding member connected to an input data storage device of the succeeding member, the combination comprising :
validation circuitry in each said member to generate a validation signal (IN_VALID, OUT_VALID) with a first state when data stored therein is valid and with a second state when data stored therein is invalid, said state defining the respective members ability to accept data;
said validation circuitry having at least one validation storage device (LVOUT) to store said validation signal of the respective member of said pair ;
said pair of stages being connected by an acceptance line which conveys an acceptance signal (IN_ACCEPT, OUT_ACCEPT) indicative of the ability of said succeeding member to load data stored in said preceding member ; and
said data storage devices (LDOUT) and validation storage devices (LVOUT) being connected to enabling circuitry to generate an enabling signal to enable loading of data and validation signals into said respective storage devices ;
whereby said processing stages are afforded enhanced flexibility in the processing of data.摘要翻译： 在视频解码和解压缩系统中，输入和输出以及定义流水线的输出之间的多个处理阶段，改进包括：响应于经由所述输入接收的数据流的令牌生成器，用于生成交互式接口 其中所述令牌的长度可变并且通过所述流水线的所述处理阶段串行地传输，并且其中所述令牌由所述处理阶段改变;以及其中，所述通用适应单元在所述处理阶段中用于数据功能。 第一双线接口，设置在一对相邻级的前一个元件和后一元件之间，包括输入数据存储装置（LDIN）和输出数据存储装置（LDOUT），在输入数据存储装置（LDIN）和输出数据存储装置 所述组合包括：每个所述成员中的验证电路，用于当存储在其中的数据有效时产生具有第一状态的验证信号（IN_VALID，OUT_VALID），并且与 第二状态，当存储在其中的数据无效时，所述状态定义各个成员接受数据的能力; 所述验证电路具有至少一个验证存储设备（LVOUT）以存储所述对的相应成员的所述验证信号; 所述一对级通过接受线路连接，所述接受线路传达指示所述后继成员的能力的接受信号（IN_ACCEPT，OUT_ACCEPT）以加载存储在所述先前成员中的数据; 并且所述数据存储设备（LDOUT）和验证存储设备（LVOUT）连接到启用电路以生成启用信号以使得能够将数据和验证信号加载到所述相应存储设备中; 由此所述处理阶段在数据处理中提供增强的灵活性。
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公开(公告)号：EP0896473A2
公开(公告)日：1999-02-10
申请号：EP98202170.1
申请日：1995-02-28
发明人： Wise, Adrian Philip , Sotheran, Martin William , Robbins, William Philip , Finch, Helen Rosemary , Boyd, Kevin James
CPC分类号： G06F13/28 , G06F12/0207 , G06F12/04 , G06F12/0607 , G06F13/1673 , G06F13/1689 , H04N19/13 , H04N19/423 , H04N19/61 , H04N19/91
摘要： A pipeline machine, comprising a plurality of processing stages, characterized by :
two successive ones of said processing stages being connected by a two-wire link, wherein said two-wire link comprises: a sender, a receiver, and a clock connected to said sender and said receiver, wherein data is transferred from said sender to said receiver upon a transition of said clock only when said sender is ready and said receiver is ready ;
wherein variable length tokens having data and control functions propagate across said two-wire link, said tokens each comprising a plurality of data words, each said word including an extension bit which indicates a presence or an absence of additional words in said token, a length of said token being determined by said extension bits; whereby said tokens are unlimited in length ;
said processing stages comprising a spatial decoder accepting an encoded data stream having a plurality of video formats carried therein, said formats including at least an MPEG format ;
a DRAM interface in said spatial decoder having a plurality of data buffers therein, and a RAM accepting data from said DRAM interface ;
a coded data buffer ;
a token generator, generating variable length tokens, a said variable length token comprising a PICTURE_END token and a FLUSH token ;
means responsive to said PICTURE_END token for performing a stop-after-picture operation for achieving a clear end to picture data decoding, for indicating the end of a picture, and for clearing the pipeline; wherein responsive to said PICTURE_END token, data is cleared from said data buffers of said DRAM interface, and data in said coded data buffer is presented to a Huffman decoder of said spatial decoder, and responsive to said FLUSH token a portion of said processing stages are reconfigured to await arrival of further data.摘要翻译： 1。一种流水线机器，包括多个处理级，其特征在于：所述处理级中的两个相继处理级通过双线链路连接，其中所述双线链路包括：发送器，接收器和连接到所述处理器的时钟 发送器和所述接收器，其中只有当所述发送器准备好并且所述接收器准备就绪时，在所述时钟转换时，数据才从所述发送器传送到所述接收器; 其中具有数据和控制功能的可变长度令牌通过所述双线链路传播，所述令牌每个包括多个数据字，每个所述字包括指示所述令牌中附加字的存在或不存在的扩展位，长度 所述令牌的所述扩展位由所述扩展位确定; 由此所述令牌的长度是无限的; 所述处理级包括空间解码器，该空间解码器接受其中携带有多个视频格式的编码数据流，所述格式至少包括MPEG格式; 所述空间解码器中的DRAM接口中具有多个数据缓冲器，以及从所述DRAM接口接收数据的RAM; 编码数据缓冲器; 令牌生成器，生成可变长度令牌，所述可变长度令牌包括PICTURE_END令牌和FLUSH令牌; 响应于所述PICTURE_END令牌执行图像后停止操作以实现图像数据解码清晰结束，指示图像结束以及清除流水线的装置; 其中响应于所述PICTURE_END令牌，从所述DRAM接口的所述数据缓冲器清除数据，并且将所述编码数据缓冲器中的数据提供给所述空间解码器的霍夫曼解码器，并且响应于所述FLUSH令牌，所述处理阶段的一部分是 重新配置以等待更多数据的到来。
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公开(公告)号：EP0674443A2
公开(公告)日：1995-09-27
申请号：EP95301301.8
申请日：1995-02-28
发明人： Wise, Adrian Philip , Sotheran, Martin William , Robbins, William Philip , Finch, Helen Rosemary , Boyd, Kevin James
CPC分类号： G06F13/28 , G06F12/0207 , G06F12/04 , G06F12/0607 , G06F13/1673 , G06F13/1689 , H04N19/13 , H04N19/423 , H04N19/61 , H04N19/91
摘要： A multi-standard video decompression apparatus has a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system.
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公开(公告)号：EP0674442A2
公开(公告)日：1995-09-27
申请号：EP95301299.4
申请日：1995-03-10
CPC分类号： G06F13/28 , G06F12/0207 , G06F12/04 , G06F12/0607 , G06F13/1673 , G06F13/1689 , H04N19/13 , H04N19/423 , H04N19/61 , H04N19/91
摘要： A multi-standard video decompression apparatus has a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token.
摘要翻译： 多标准视频解压缩装置具有通过布置为流水线处理机的两线接口互连的多个级。 控制令牌和数据令牌通过单个双线接口，以承载格式携带控制和数据。 令牌解码电路位于某些阶段中，用于将某些令牌识别为与该级相关的控制令牌，并沿着管道传递未被识别的控制令牌。 重新配置处理电路定位在选定的阶段，并且响应于识别的控制令牌，以重新配置这样的阶段来处理所识别的数据令牌。
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