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公开(公告)号：EP1091616A1
公开(公告)日：2001-04-11
申请号：EP00919158.6
申请日：2000-04-24
IPC分类号： H04R7/14
CPC分类号： H04R7/14 , H04R2307/029
摘要： A speaker diaphragm 10 is provided having an improved quality of radiation sounds and a good outer appearance. The speaker diaphragm has in its slanted area projections typically represented by a peak line 4 and recesses typically represented by a bottom line 5. The projection typically represented by the peak line extends radially from the central area to the edge portion, and curves along the circumferential direction as it comes near to the edge portion. While the speaker diaphragm 10 vibrates at a large amplitude and moves toward the bottom side thereof, a rotation force is applied to air which is likely to concentrate upon the central area to thereby lower the air pressure to the central area. The speaker diaphragm 10 has a three-dimensional structure like a screw propeller so that the mechanical strength of the speaker diaphragm 10 can be increased over the whole area thereof and division vibrations can be suppressed. The speaker diaphragm is manufactured by ejection molding of material containing polypropylene as it main composition so that a variety of colors can be easily used during manufacture processes. In cooperation with the unique structure like the screw propeller, a strong visual impression is given.
摘要翻译： 扬声器振动膜10具有改善的辐射声音质量和良好的外观。 扬声器振膜在其倾斜区域中具有通常由峰值线4表示的投影和通常由底线5表示的凹陷。典型地由峰值线表示的投影从中心区域径向地延伸至边缘部分，并且沿着圆周 方向靠近边缘部分。 当扬声器振动膜片10振动很大并向其底侧移动时，旋转力施加到可能集中在中央区域的空气上，从而降低空气压力到中央区域。 扬声器振动膜10具有螺旋桨这样的三维结构，因此扬声器振动膜10的机械强度可以在其整个区域增加，并且可以抑制分割振动。 扬声器振动膜通过喷射模制包含聚丙烯的材料作为其主要成分来制造，使得在制造过程中可以容易地使用各种颜色。 与螺旋桨这样的独特结构相结合，给人一种强烈的视觉印象。
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公开(公告)号：EP0685937B1
公开(公告)日：2001-04-04
申请号：EP95108475.5
申请日：1995-06-01
发明人： Honma, Souichi
IPC分类号： H03H21/00
CPC分类号： H03H21/0012
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公开(公告)号：EP1081903A1
公开(公告)日：2001-03-07
申请号：EP99922481.9
申请日：1999-05-13
IPC分类号： H04L27/18
CPC分类号： H04L1/0052 , H04L1/0054 , H04L1/006 , H04L27/2332 , H04L2027/0032 , H04L2027/0057
摘要： A BS digital broadcast receiver having no 8PSK demapper and a less number of delay circuits for Trellis encoding. A QPSK baseband signal based upon a reception signal point position of an absolute-phased baseband demodulation signal is Viterbi-decoded by a Viterbi-decoder 6. An output of the Viterbi-decoder is convolution-reencoded by a convolution encoder 7. Upper four bits of phase error data are searched from a phase error table 31 for carrier reproduction in accordance with a phase difference between 0 degree and a phase of a phase error detection reception signal point position. The upper four bits are delayed by delay circuits 81 to 84 by a total sum of a time taken to Viterbi-decode and a time taken to convolution-encode. The delayed outputs are demapped by a demapped value conversion circuit 9. A code TCD2 determined from the demapped output and convolution encode output is output as an MSB of a Trellis 8PSK decode output from an MSB code judging/error detecting circuit 10.
摘要翻译： 没有8PSK解映射器的BS数字广播接收机和用于网格编码的较少数量的延迟电路。 基于绝对相位基带解调信号的接收信号点位置的QPSK基带信号由维特比解码器6进行维特比解码。维特比解码器的输出由卷积编码器7进行卷积重新编码。高四位 根据0度与相位误差检测接收信号点位置的相位之间的相位差，从用于载波再现的相位误差表31中搜索相位误差数据。 延迟电路81至84通过维特比解码所花费的时间和对卷积编码所花费的时间的总和来延迟高4位。 延迟的输出被去映射值转换电路9解映射。从解映射的输出和卷积编码输出确定的代码TCD2被输出为从MSB代码判断/错误检测电路10的格子8PSK解码输出的MSB。
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54.发明公开
公开(公告)号：EP1054537A1
公开(公告)日：2000-11-22
申请号：EP98955991.9
申请日：1998-11-30
IPC分类号： H04L27/22
CPC分类号： H04L27/2332 , H04L2027/003 , H04L2027/0057 , H04L2027/0081 , H04L2027/0095
摘要： There is proceeded hierarchical transmission digital demodulator capable of stable sync capture and stable demodulation through setting of a demodulation operation in accordance with a reception C/N value. A CNR measuring circuit 10 receives a demodulation output from an arithmetic circuit 1 and measures a reception C/N value. During a period until a sync is captured, a carrier is reproduced in accordance with the demodulation output that a modulated wave in a header section and a modulated wave of burst symbol signal.
After the sync is captured, at an intermediate C/N value the carrier is reproduced in accordance with the demodulation output of the header section, burst symbol signal and QPSK signal and in accordance with output from a logical gate circuit 11, and at high and low C/N values the carrier is reproduced by setting high a carrier reproduction loop gain of a gain control circuit 8 in accordance with a signal from the logical gate circuit 11.摘要翻译： 通过根据接收C / N值设置解调操作，能够进行稳定的同步捕获和稳定的解调的分级发送数字解调器。 CNR测量电路10接收来自运算电路1的解调输出并测量接收C / N值。 在捕获同步之前的一段时间内，根据解调输出再现载波，以便在报头部分中的调制波和突发符号信号的调制波。 在捕获同步之后，以中间C / N值，根据标题部分的解调输出，突发符号信号和QPSK信号，并根据逻辑门电路11的输出，以及在高和 根据来自逻辑门电路11的信号，通过设置增益控制电路8的高载波再生环路增益来使载波再生的低C / N值。
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公开(公告)号：EP1039710A1
公开(公告)日：2000-09-27
申请号：EP98961593.5
申请日：1998-12-25
发明人： KATOH, Hisakazu , HASHIMOTO, Akinori, NHK Hosogijutsukenkyusyo , SAITO, Tomohiro, NHK Hosogijutsukenkyusyo , MINEMATSU, Fumiaki, NHK Hosogijutsukenkyusyo , SHIRAISHI, Kenichi , HORII, Akihiro , MATSUDA, Shoji , SHINJO, Soichi
IPC分类号： H04L27/22
CPC分类号： H04L27/2273
摘要： A carrier reproduction circuit which can perform stable carrier reproduction even when reception takes place with low C/N values is provided. The reception phase of the demodulated known-pattern reception signal is detected with a frame synchronizing timing circuit (4), and based on the detected reception phase, either the phase difference table of absolute phase having one convergence point or the phase difference table of the phase rotated from the absolute phase by 180°, which are included in a carrier reproduction phase difference detecting circuit (8), is selected, and from the selected phase difference table the output based on the phase difference between the phase obtained from the signal point position of the reception signal and the phase convergence point is obtained, and thus carrier reproduction is implemented by undergoing the reproduced carrier frequency control via an AFC circuit (10) so that the phase obtained from the signal point position coincides with the phase convergence point.
摘要翻译： 提供即使在接收发生时具有低C / N值也能够执行稳定的载波再现的载波再现电路。 利用帧同步定时电路（4）检测解调后的已知模式接收信号的接收相位，并且根据检测到的接收相位，具有一个收敛点的绝对相位的相位差表或者具有一个收敛点的相位差表 选择包含在载波再现相位差检测电路（8）中的从绝对相位旋转180°的相位，并且从所选择的相位差表中选择基于从信号点获得的相位之间的相位差的输出 获得接收信号和相位收敛点的位置，从而通过经由AFC电路（10）经历再现的载波频率控制来实现载波再现，使得从信号点位置获得的相位与相位收敛点一致。
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公开(公告)号：EP0613322B1
公开(公告)日：2000-08-16
申请号：EP94101384.9
申请日：1994-01-31
CPC分类号： H04R9/045 , H04R9/025 , H04R2209/022
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公开(公告)号：EP1023721A1
公开(公告)日：2000-08-02
申请号：EP98943091.3
申请日：1998-09-22
IPC分类号： G11B7/14
摘要： In a CD-ROM readout system wherein five adjacent tracks of a CD-ROM (1) are separately illuminated by the five light beams (31-35) of an optical pickup (2), in which a recorded data readout system simultaneously reads the recorded data of the separate tracks by detecting the received light outputs of the returned beams, and outputs the data in the sequence in which it was recorded; for example, if the data from the light beam (35), becomes unreadable by the recorded data readout system, the system will read the recorded data using the remaining four light beams, (31-34). This readout is performed in recurring operations in which data is read for approximately one revolution of the CD-ROM (1); then, after there are no longer any gaps in the [combined] data read out by light beans (31-34) the pickup is track-jumped forward by approximately two tracks. At this point the recorded data is again read for one revolution, and the process repeats.
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公开(公告)号：EP1004117A1
公开(公告)日：2000-05-31
申请号：EP98936717.2
申请日：1998-08-10
发明人： IMAI, Tsutomu , HAGA, Yosuke , SASADA, Takeharu , MASUDA, Shinji , ONO, Atuomi , MURAKAMI, Midori
CPC分类号： G11B33/08 , B60R11/0211
摘要： A floating chassis support mechanism is provided which can thin a disc reproduction apparatus. In the floating chassis support mechanism for a disc reproduction apparatus for supporting a floating chassis (3) with springs and dampers (4) vertically from the opposite side of a loaded disc (15), the damper (4) is disposed outside of a projection area of the disc, and an area of the floating chassis (3) supported by the dampers (4) is retracted toward the disc side more than a lower surface of the disc (15).
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公开(公告)号：EP0993160A1
公开(公告)日：2000-04-12
申请号：EP98921724.5
申请日：1998-05-20
发明人： HORII, Akihiro , SHIRAISHI, Kenichi
IPC分类号： H04L27/227
CPC分类号： H04L27/2273 , H03J2200/02 , H04L1/206
摘要： A carrier reproducing circuit capable of reproducing a carrier quickly, wherein: a signal point arrangement converting circuit (14) detects the signal point arrangement of a demodulating baseband signal of a carrier when the carrier has a frequency different by a predetermined value from the center frequency of the modulated wave; a variance calculating circuit (15) calculates, based on the signal point arrangement, the number of times that the variance exceeds a preset threshold per unit time; a CN determination circuit (16) determines the reception CN ratio based on the number of times; a scanning step frequency width converting circuit (19) sets a frequency width changed by one step based on the determined reception CN ratio; the carrier for demodulating is sent out by changing oscillation frequencies of oscillators (6, 7) through an AFC circuit (20) based on the present frequency width; and when a carrier synchronization judging circuit (18) detects that the number of times decreases to a value equal to or smaller than a threshold determined based on the reception CN ratio, the scanning by the AFC circuit (20) is stopped.
摘要翻译： 一种能够快速再现载波的载波再现电路，其中：信号点排列转换电路（14）检测载波的解调基带信号的信号点排列，当载波具有与中心频率不同的预定值的频率时 的调制波; 方差计算电路（15）基于信号点排列来计算每单位时间的方差超过预设阈值的次数; CN确定电路（16）基于次数确定接收CN比; 扫描步长频率变换电路（19）基于所确定的接收CN比设定改变了一步的频率宽度; 通过基于当前频率宽度通过AFC电路（20）改变振荡器（6,7）的振荡频率来发送用于解调的载波; 并且当载波同步判断电路（18）检测到次数减少到等于或小于基于接收CN比确定的阈值的值时，由AFC电路（20）的扫描停止。
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公开(公告)号：EP0985304A1
公开(公告)日：2000-03-15
申请号：EP98919561.5
申请日：1998-05-12
发明人： KATSUMOTO, Hiroshi
IPC分类号： H04L27/26
CPC分类号： H04L27/2657 , H04L27/2675 , H04L2027/0028 , H04L2027/0065 , H04L2027/0079 , H04L2027/0089
摘要： A receiver is provided which can perform normal reception even under strict environments such as multi-path environments. A frequency offset detector (7) detects a frequency offset amount in accordance with a phase reference symbol. The detected frequency offset value is integrated by an integrator (17). The integrated value is compared by a comparator (18) with a predetermined threshold value range. If the integrated value output from the integrator is in the threshold value range, a frequency offset value amount detected by another frequency offset detector (8) in accordance with a phase difference of a delay-detection output is selected by a switch circuit (10). If the integrated value is not in the threshold value range, the frequency offset value detected by the frequency offset detector (7) is selected by the switch circuit (10). In accordance with each selected frequency offset value, automatic frequency control of the receiver is performed.
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