METHOD AND APPARATUS FOR DESIGNING LOW DENSITY PARITY CHECK CODE WITH MULTIPLE CODE RATES, AND INFORMATION STORAGE MEDIUM THEREOF
    51.
    发明公开
    METHOD AND APPARATUS FOR DESIGNING LOW DENSITY PARITY CHECK CODE WITH MULTIPLE CODE RATES, AND INFORMATION STORAGE MEDIUM THEREOF 审中-公开
    方法和设备LDPC码的多个码速率和信息存储介质THEREFOR设计

    公开(公告)号:EP2156564A1

    公开(公告)日:2010-02-24

    申请号:EP08712171.1

    申请日:2008-01-23

    发明人: HWANG, Sung-Hee

    IPC分类号: H03M13/11

    摘要: A method and apparatus for generating a low density parity check (LDPC) code having a variable code rate, the method of generating the LDPC code having a variable code rate including: generating a first parity check matrix by combining a parity matrix or a parity check matrix and a first information word matrix; and generating a second parity check matrix by combining the first parity check matrix and a second information word matrix. According to the method and apparatus, error correction performance is enhanced.

    摘要翻译: 通过组合的奇偶矩阵或奇偶校验产生第一奇偶校验矩阵:一个用于产生具有可变编码率,产生具有可变编码率包括LDPC码的方法的低密度奇偶校验(LDPC)码的方法和装置 矩阵和第一信息字矩阵; 以及通过组合所述第一奇偶校验矩阵和第二信息字矩阵产生第二奇偶校验矩阵。 。根据该方法和装置,纠错性能提高。

    INFORMATION RECORDING MEDIUM, RECORDING/RE¬ PRODUCING APPARATUS AND RECORDING/REPRODUCING METHOD
    53.
    发明公开
    INFORMATION RECORDING MEDIUM, RECORDING/RE¬ PRODUCING APPARATUS AND RECORDING/REPRODUCING METHOD 有权
    信息记录介质,记录/重制装置和记录/复制方法

    公开(公告)号:EP1774525A1

    公开(公告)日:2007-04-18

    申请号:EP05773923.7

    申请日:2005-08-01

    IPC分类号: G11B20/12

    摘要: An information recording medium, a recording and/or reproducing apparatus and a recording and/or reproducing method are provided. The recording apparatus includes: a write/read unit for recording data on an information storage medium in which a user data area for writing user data and a spare area for replacing a defect occurring in the user data area are disposed, and a replacement recording block to replace an original recording block recorded in the user data area is recorded in a non-recorded area of the spare area or the user data area; and a control unit for controlling the write/read unit so that a replacement entry indicating that part of the recording block is replaced is recorded on the storage medium. As a result, data reproduction time can be advantageously reduced so as to improve system performance, particularly, in a system where data replacement by logical overwrite (LOW) is implemented both in a user data area and a spare area, or in a system performing defect management.

    摘要翻译: 提供信息记录介质,记录和/或再现装置以及记录和/或再现方法。 该记录设备包括:用于在信息存储介质上记录数据的写入/读取单元,在该信息存储介质中设置用于写入用户数据的用户数据区域和用于替换在用户数据区域中发生的缺陷的备用区域,以及替换记录块 将替换记录在用户数据区域中的原始记录块记录在备用区域或用户数据区域的未记录区域中; 以及控制单元,用于控制写入/读取单元,使得指示该部分记录块被替换的替换条目被记录在存储介质上。 结果,可以有利地减少数据再现时间,从而提高系统性能,特别是在通过逻辑覆盖(LOW)进行数据替换的系统既在用户数据区域中也在备用区域中执行,或者在系统执行 缺陷管理。

    APPARATUS TO GENERATE A BIT CLOCK AND A METHOD OF GENERATING THE BIT CLOCK
    58.
    发明公开
    APPARATUS TO GENERATE A BIT CLOCK AND A METHOD OF GENERATING THE BIT CLOCK 审中-公开
    DEVICE用于产生比特时钟和方法用于产生比特时钟

    公开(公告)号:EP1586095A1

    公开(公告)日:2005-10-19

    申请号:EP04702872.5

    申请日:2004-01-16

    发明人: HWANG, Sung-Hee

    IPC分类号: G11B20/14

    CPC分类号: G11B20/1403

    摘要: An apparatus and a method to accurately generate a bit clock synchronized with digital data. The apparatus includes an edge detecting unit, a first edge counter, a second edge counter, a first counter, and a bit clock generating unit. The edge detecting unit detects edges of the digital signal. The first edge counter counts a number of the detected edges during a first period. The second edge counter counts the number of the detected edges during a second period. The first counter is reset and counts a system clock if one of the edges is detected during the first period. The bit clock generating unit generates a bit clock based on a count valAn apparatus and a method to accurately generate a bit clock synchronized with digital data. The apparatus includes an edge detecting unit, a first edge counter, a second edge counter, a first counter, and a bit clock generating unit. The edge detecting unit detects edges of the digital signal. The first edge counter counts a number of the detected edges during a first period. The second edge counter counts the number of the detected edges during a second period. The first counter is reset and counts a system clock if one of the edges is detected during the first period. The bit clock generating unit generates a bit clock based on a count value of the first counter or a channel bit interval, if one of the first edge count value and the second edge count value is equal to a first predetermined value.