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61.发明公开
公开(公告)号：EP0291557A1
公开(公告)日：1988-11-23
申请号：EP87107471.2
申请日：1987-05-22
申请人： Honeywell Bull Inc.
发明人： Smith, Michael D. , Dunwell, Llewelyn S. , Lemay, Richard A. , Miller, Robert C. , Staplin, Theodore R. Jnr. , Woods, William E. , Curley, John L.
IPC分类号： G06F12/10
CPC分类号： G06F12/1054
摘要： A data processing system includes a central processor unit (CPU), a main memory and a memory management unit (MMU). Information is stored in main memory in segments, each segment being identified by a segment descriptor stored in a translation table in the MMU. Logical addresses from the CPU address segment descriptors in the MMU's translation table. These segment descriptors include the physical address of the location in main memory of the first word of the segment. If the segment descriptor is not in the translation table location, then the MMU operation is suspended while the segment descriptor is demand fetched from main memory.
摘要翻译： 数据处理系统包括中央处理器单元（CPU），主存储器和存储器管理单元（MMU）。 信息以片段存储在主存储器中，每个段由存储在MMU中的转换表中的段描述符标识。 MMU翻译表中CPU地址段描述符的逻辑地址。 这些段描述符包括段的第一个单词的主存储器中的位置的物理地址。 如果段描述符不在转换表位置，则MMU操作被暂停，而段描述符是从主存储器获取请求。
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公开(公告)号：EP0197559A3
公开(公告)日：1988-08-31
申请号：EP86104902
申请日：1986-04-10
申请人： Honeywell Bull Inc.
IPC分类号： G06F09/38
CPC分类号： G06F9/3885
摘要： A data processing system includes the functionality of a commercial instruction processor, a scientific instruction processor and a basic instruction processor integrated into a single semiconductor logic element.
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公开(公告)号：EP0178671A3
公开(公告)日：1988-08-17
申请号：EP85113207
申请日：1985-10-17
申请人： Honeywell Bull Inc.
IPC分类号： G06F09/26
摘要： A method and apparatus for a microinstruction controi- led unit having multiple subunits which are controlled bv microoperations encoded within microinstructions from a control store. One master subunit controls the order in which the microinstructions are executea by generating the address of the next microinstruction to be read from the control store. The method provides for the overlapping of the execution of a current microinstruction while the next microinstruction is being addressed and read from the control store. The control store is divided into control substores with each control substore iocated near the subunit which executes the microcperations stored in its associated control substore. Subunits can atrect the order of microinstruction execution by causing a trad in the master subunit which will cause the next microinstruction to be read from a predefined address within the control store If required, the master subunit can read in status information from the subunits in order to determine the condition within the subunits that caused tne trap to occur. A means is provided for storing a return address which aliows to execution to continue at the next microinstruction that wot have executed had a trap not occurred.
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公开(公告)号：EP0251234A3
公开(公告)日：1988-07-20
申请号：EP87109194
申请日：1987-06-26
申请人： Honeywell Bull Inc.
CPC分类号： G06F9/4812 , G06F13/26
摘要： Apparatus is included within the bus interface circuits of each processing unit of a multiprocessing system which connect in common with the other units of the system to an asynchronous system bus. The apparatus and interrupt couples to the processing unit's level register and interrupt circuits. In response to a command specifying a level change, the apparatus conditions these circuits to store level and interrupt signals applied to the system bus as part of such CPU command during a bus cycle of operation granted to the processing unit on a priority basis. This ensures the reliable switching between interrupt levels and the notification of such level changes to the other units of the system without interference from other processing units.
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公开(公告)号：EP0264077A2
公开(公告)日：1988-04-20
申请号：EP87114769.0
申请日：1987-10-09
申请人： Honeywell Bull Inc.
IPC分类号： G06F7/00
CPC分类号： G06F7/78
摘要： A buffer address register is disclosed having multiple address input ports and capable of storing a plurality of addresses. Address loading operations are over-lapped with address reading operations to speed up the rate at which addresses may be stored in and retrieved from the register. When the register is full of addresses it provides an indication which permits: the address already stored in the register to be read out and stored in an external memory, then additional addresses to be stored in the register, and subsequently the addresses transferred to the memory for storage to be transferred to the buffer address register for read out.
摘要翻译： 公开了具有多个地址输入端口并且能够存储多个地址的缓冲器地址寄存器。 地址加载操作与地址读取操作重叠，以加快地址可以从寄存器存储和检索的速率。 当寄存器充满地址时，它提供一个指示，允许：已经存储在寄存器中的地址被读出并存储在外部存储器中，然后将要存储在寄存器中的附加地址，以及随后传送到存储器的地址 用于存储被传送到缓冲地址寄存器以进行读出。
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公开(公告)号：EP0055128B1
公开(公告)日：1988-02-17
申请号：EP81306043.1
申请日：1981-12-22
申请人： Honeywell Bull Inc.
CPC分类号： G06F9/226
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公开(公告)号：EP0206320A3
公开(公告)日：1987-12-09
申请号：EP86108613
申请日：1986-06-24
申请人： Honeywell Bull Inc.
发明人： Noyes, Robert W.
IPC分类号： H01R13/74 , H01R13/627
CPC分类号： H01R13/748 , H01R13/627
摘要： A novel method and apparatus for latching and locking D-type electrical connectors. In one embodiment a novel «bud-stud» is utilized to replace pior art isoblocks or prior art hexagonal nuts. The bud-stud is capable of mating with either a prior art screw-type or spring-loaded latching arm to latch and lock the electrical connectors to each other and to a bulkhead.
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公开(公告)号：EP0049627B1
公开(公告)日：1987-12-09
申请号：EP81304592.9
申请日：1981-10-05
申请人： Honeywell Bull Inc.
CPC分类号： H04L7/042
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公开(公告)号：EP0234038A2
公开(公告)日：1987-09-02
申请号：EP86117605.5
申请日：1986-12-17
申请人： Honeywell Bull Inc.
IPC分类号： G06F12/12
CPC分类号： G06F12/123
摘要： A least recently used replacement level generator is constructed to include n number of register stages connected in tandem. A comparison circuit associated with each stage except the last stage compare the contents of that stage with an input level value which is to be loaded into the input stage. In the absence of an identical comparison, each stage generates a shift enable signal which is passed on to the next succeeding stage. An identical comparison inhibits the generation of the shift enable signal. Therefore, when a clock signal is applied to the device, register stages, in the presence of a control signal, cause the input level to be loaded into the input stage while the level contents of the register stages are simultaneously shifted through successive stages including the register stage whose contents are identical to the input level under the control of the shift enable signal. The contents of the output register stage accurately and instantaneously defines the least recently used replacement level for use by a cache memory.
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公开(公告)号：EP0184857A2
公开(公告)日：1986-06-18
申请号：EP85115932.7
申请日：1985-12-13
申请人： Honeywell Bull Inc.
IPC分类号： G09G1/28
CPC分类号： G09G5/022
摘要： A color display graphics system includes three bit map memories for storing bits representing red, green and blue colors respectively. Combinations of bits from the same address locations of each bit map memory display a pixel which could be any one of eight colors: black, bleu, green, cyan, red, magenta, yellow or white. A read only memory (ROM) stores patterns made up of sixteen bits in a four-by-four matrix for each of the red, green and blue colors. The 16-bit matrices are stored in their respective bit map memories for subsequent color display. Combinations of matrices may be used to show shades of the above eight colors and the mixing of any of those shades.
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