公开(公告)号：EP2432020A1

公开(公告)日：2012-03-21

申请号：EP10774830.3

申请日：2010-04-27

申请人： Sumitomo Electric Industries, Ltd.

发明人： WADA, Keiji ,  HARADA, Shin ,  MASUDA, Takeyoshi ,  HONAGA, Misako ,  SASAKI, Makoto ,  NISHIGUCHI, Taro ,  NAMIKAWA, Yasuo ,  FUJIWARA, Shinsuke

IPC分类号： H01L29/12 ,  H01L21/02 ,  H01L21/20 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L29/7802 ,  C30B23/00 ,  C30B29/36 ,  C30B33/06 ,  H01L21/02378 ,  H01L21/02529 ,  H01L21/2007 ,  H01L29/045 ,  H01L29/0878 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7395

摘要： A MOSFET (100), which is a semiconductor device allowing for reduced on-resistance while restraining stacking faults from being produced due to heat treatment in a device manufacturing process, includes: a silicon carbide substrate (1); an active layer (7) made of single-crystal silicon carbide and disposed on one main surface of the silicon carbide substrate (1); a source contact electrode (92) disposed on the active layer (7); and a drain electrode (96) formed on the other main surface of the silicon carbide substrate (1). The silicon carbide substrate (1) includes: a base layer (10) made of silicon carbide; and a SiC layer (20) made of single-crystal silicon carbide and disposed on the base layer (10). Further, the base layer (10) has an impurity concentration greater than 2 × 10 19 cm 13 , and the SiC layer (20) has an impurity concentration greater than 5 × 10 18 cm 13 and smaller than 2 × 10 19 cm -3 .

摘要翻译： 本发明公开了一种MOSFET（100），该器件是允许降低导通电阻同时抑制由于器件制造工艺中的热处理而产生堆叠故障的半导体器件，包括：碳化硅衬底（1）; 由单晶碳化硅制成并设置在碳化硅衬底（1）的一个主表面上的有源层（7）; 设置在有源层（7）上的源极接触电极（92）; 和形成在碳化硅衬底（1）的另一个主表面上的漏电极（96）。 碳化硅衬底（1）包括：由碳化硅制成的基底层（10） 和由单晶碳化硅制成并设置在基层（10）上的SiC层（20）。 此外，基极层（10）的杂质浓度大于2×1019cm13，并且SiC层（20）的杂质浓度大于5×1018cm13且小于2×1019cm-3。