利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

189 条记录 (耗时 0.009 秒)

    CPU-bus controller
    61.
    发明公开
    CPU-bus controller 失效
    CPU-Bussteuerschaltung。

    公开(公告)号：EP0423036A2

    公开(公告)日：1991-04-17

    申请号：EP90402847.9

    申请日：1990-10-11

    申请人： AST RESEARCH, Inc.

    发明人： Larson, Ronald J.

    IPC分类号： G06F13/20 ,  G06F13/40

    CPC分类号： G06F13/423

    摘要： A synchronous bus controller which provides a functional control link between one or more microprocessors and an asychronous main input/output bus is provided. The bus controller includes a state machine and data bus width determining logic enabling the bus controller to initiate and control access operations between microprocessors and accessible devices on the main input/output bus when the microprocessor and the accessed device may have different data bus widths. The bus controller includes logic circuitry to determine the number of access cycles required to complete a requested access operation and detects the last access cycle of a current access operation to terminate an access operation and provide a ready signal to the microprocessor indicating that the bus controller is ready for the next access request.

    摘要翻译： 提供一种提供一个或多个微处理器与异步主输入/输出总线之间的功能控制链路的同步总线控制器。 总线控制器包括状态机和数据总线宽度确定逻辑，当微处理器和被访问的设备可能具有不同的数据总线宽度时，总线控制器能够启动和控制微处理器与主输入/输出总线上的可访问设备之间的访问操作。 总线控制器包括逻辑电路，用于确定完成请求的访问操作所需的访问周期的数量，并且检测当前访问操作的最后访问周期以终止访问操作，并向微处理器提供就绪信号，指示总线控制器是 准备下一次访问请求。

    Bus arbiter for a data processing system having an input/output channel
    62.
    发明公开
    Bus arbiter for a data processing system having an input/output channel 失效
    总线仲裁器用于具有输入/输出通道的数据处理系统。

    公开(公告)号：EP0192838A2

    公开(公告)日：1986-09-03

    申请号：EP85115701.6

    申请日：1985-12-10

    申请人： International Business Machines Corporation

    发明人： Irwin, John W.

    IPC分类号： G06F13/20

    CPC分类号： G06F13/20 ,  G06F13/36

    摘要： A data processing system having a main processing unit, a memory subsystem, and a co-processor selectively connectable to said memory subsystem through an Input/Output Channel Controller which includes a control means for arbitrating access to the I/0 bus among the co-processor and the other I/O devices form access to the bus. Since the co-processor runs programs stored in the memory subsystem, there is a tendency for the co-processor to monopolize the bus with instruction fetch cycles, thereby excluding other I/O devices from access to the bus. The control means for arbitrating responds to requests on the basis of a linear priority scheme in which the co-processor has the lowest priority. Each device, except the co-processor, is permitted to keep control of the bus until it voluntarily relinquishes it. The co-processor, on the other hand, relinquishes control of the bus in response to a request for access by any higher operator. However, control is returned automatically to the co-processor in the absence of any other request, since the co-processor continually raises its access request line.