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157 条记录 (耗时 0.019 秒)

    DIFFERENTIAL PAIR GAIN CONTROL STAGE
    71.
    发明公开
    DIFFERENTIAL PAIR GAIN CONTROL STAGE 失效
    增益控制水平FOR差分放大器

    公开(公告)号：EP0909479A1

    公开(公告)日：1999-04-21

    申请号：EP98920924.0

    申请日：1998-04-30

    申请人： Raytheon Company

    发明人： CHEN, Ricky, Y. ,  LINDER, Lloyd, F. ,  DEVENDORF, Don, C. ,  GORDER, Matthew, S.

    IPC分类号： H03G3 ,  H03D7 ,  H03G1

    CPC分类号： H03G1/0023 ,  H03D7/1408 ,  H03D7/1433 ,  H03D7/1441 ,  H03D7/1458 ,  H03D7/1491 ,  H03D2200/0025 ,  H03D2200/0047

    摘要： A 'gain control differential pair' (GCDP) (10) conducts current in response to a differential drive signal, with the gain of a signal path formed via the current circuit of one of its transistors controlled by the drive signal. The GCDP is preferably driven with a drive circuit (20) that receives a symmetrical input signal and produces an offset differential drive signal which has the effect of keeping one of the GCDP's transistors turned off over a wider portion of a symmetrical input signal's voltage range, thereby reducing GCDP-caused noise. One or more GCDPs are implemented as part of a Gilbert mixer (30) to regulate the amount of RF current that flows between the mixer's output and input stages, which eliminates the need to provide gain control in other circuits fed by the mixer. When driven with an offset drive signal, the Gilbert mixer simultaneously provides gain control, low distortion, low power consumption and excellent LO/RF isolation.

    Receiver
    73.
    发明授权
    Receiver 失效
    接收器

    公开(公告)号：EP0594403B1

    公开(公告)日：1998-06-24

    申请号：EP93308310.7

    申请日：1993-10-19

    申请人： NEC CORPORATION

    发明人： Minami, Yoichiro, c/o NEC Corporation

    IPC分类号： H03D3/24 ,  H04Q7/06

    CPC分类号： H03D3/241 ,  H03D2200/0047 ,  H03D2200/0082 ,  H04W52/0229 ,  H04W88/022 ,  Y02D70/144

    摘要： In a receiver for use in demodulating a modulated wave modulated by a digital data signal arranged within a preselected channel to produce a reproduced data signal by the use of a local frequency signal of a local frequency, a VCO and a PLL circuit are intermittently put into active states with reference to an offset frequency between a channel frequency and the local frequency. The PLL circuit is put into the active state for a time interval determined by the offset frequency before reception of the preselected channel while the VCO is put into the active state during the active state of the PLL circuit and during reception of the preselected channel. The duration of the active state in the PLL circuit becomes long when the offset frequency does not fall within a predetermined range determined by predetermined offset frequencies and, otherwise, the duration of the active state in the PLL circuit becomes short. The offset frequency is detected by a frequency detector which produces a control signal appearing only when the offset frequency is present outside of the predetermined range. The control signal is sent to a control circuit for controlling battery saving operations of the VCO and the PLL circuit.

    RECEIVING CIRCUIT
    74.
    发明公开
    RECEIVING CIRCUIT 失效
    EMPFANGSSCHALTUNG

    公开(公告)号：EP0742647A1

    公开(公告)日：1996-11-13

    申请号：EP95938618.6

    申请日：1995-11-30

    申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

    发明人： OHTA, Gen-ichiro ,  INOKAI, Kazunori ,  SASAKI, Fujio, 101, Daiyaparesu Nakayama No. 2

    IPC分类号： H04B1/26

    CPC分类号： H04B1/0032 ,  H03D1/2245 ,  H03D7/165 ,  H03D2200/0047 ,  H03D2200/005 ,  H03D2200/0082 ,  H03F3/45475 ,  H03F3/50 ,  H03F2200/537 ,  H04B1/0003 ,  H04B1/123 ,  H04B1/26 ,  H04B5/0093 ,  Y02D70/40 ,  Y02D70/42

    摘要： A receiving circuit mainly available in a digital modulation type communication system having a plurality of channels, which is capable of reducing power in a receiving system, simplifying the circuit and reducing the power consumption. Upside and downside frequencies corresponding to a central value between channels are separately supplied from a local frequency signal generating circuit 4 to first and second frequency converting circuits 2, 3 so that two output signals are developed with respect to one of a desired wave, upside channel and downside channel. The desired wave present in common in the first and second frequency converting circuits 2, 3 is extracted in a common wave extracting circuit 5, and a frequency offset of ωo existing in the output of the common wave extracting circuit 5 is removed a frequency offset circuit 6 and further an unnecessary frequency component is filtered by a filter 8. In addition, the common wave extracting circuit 5 has transformers and, using its inductances, raises the difference between the common wave and the non-common wave within the circuit to more than two times that of a prior art.

    摘要翻译： 主要可用于具有多个信道的数字调制型通信系统中的接收电路，其能够降低接收系统的功率，简化电路并降低功耗。 对应于通道之间的中心值的上升和下降频率从本地频率信号发生电路4分别提供给第一和第二频率转换电路2,3，使得两个输出信号相对于所需波形，上行通道 和下行通道。 在公共波提取电路5中提取在第一和第二频率转换电路2,3中共同存在的期望的波，并且公共波提取电路5的输出中存在的ωo的频率偏移被去除频率偏移 电路6，另外，不需要的频率分量被滤波器8滤波。此外，公共波提取电路5具有变压器，并且使用其电感将公共波与电路内的非公共波之间的差异提高到更多 是现有技术的两倍以上。

    Direct conversion receivers
    75.
    发明公开
    Direct conversion receivers 失效
    DIREKT-Mischempfänger。

    公开(公告)号：EP0647016A1

    公开(公告)日：1995-04-05

    申请号：EP94306737.1

    申请日：1994-09-14

    申请人： PLESSEY SEMICONDUCTORS LIMITED

    发明人： Mapleston, David Bernard

    IPC分类号： H03D7/16 ,  H04B1/30

    CPC分类号： H04B1/30 ,  H03D7/165 ,  H03D2200/0047

    摘要： A radio receiver arrangement utilising direct conversion or conversion to a low IF frequency, in which the local oscillator signal is frequency modulated to avoid the possibility of the local oscillator frequency drifting into a zero beat frequency region where only a d.c. voltage will be obtained from the mixer.

    摘要翻译： 一种使用直接转换或转换为低IF频率的无线电接收器装置，其中本地振荡器信号被频率调制，以避免本地振荡器频率漂移到仅零直流的零拍频率区域的可能性。 将从混合器获得电压。

    D.C. offset compensation in a radio receiver
    78.
    发明公开
    D.C. offset compensation in a radio receiver 失效
    Offset-Gleichspannungskompensation einesFunkempfängers。

    公开(公告)号：EP0474615A2

    公开(公告)日：1992-03-11

    申请号：EP91850216.2

    申请日：1991-09-05

    申请人： TELEFONAKTIEBOLAGET L M ERICSSON

    发明人： Dent, Paul Wilkinson

    IPC分类号： H04B1/30 ,  H04L27/22 ,  H04L25/06

    CPC分类号： H04L25/062 ,  H03D3/008 ,  H03D7/165 ,  H03D2200/0047 ,  H03D2200/0082 ,  H03D2200/009 ,  H04B1/30 ,  H04L7/046

    摘要： A zero-IF radio receiver eliminates DC offset without distortion or loss of the low-frequency and DC components of the received or desired signal by initially differentiating the received signal to filter out the DC offset. The signal is amplified to a suitable level and then integrated to recapture the original DC and low frequency signal components. The integration essentially restores the filtered components to the original value in the amplified signal using an arbitrary constant of integration of bounded magnitude to generate a restored signal. Using various techniques that exploit predetermined signal patterns or inherent signal properties of the desired signal, the DC offset can be reasonably estimated. The DC offset estimate is then subtracted out of the restored signal leaving the amplified, received signal substantially free from distortion. An advantageous method for differentiating and digitizing the received signal uses the technique of companded delta modulation.

    摘要翻译： 零中频无线电接收器通过初始地对接收信号进行微分以滤除直流偏移，从而消除了直流偏移而不会使接收到​​或期望信号的低频和直流分量失真或丢失。 信号被放大到合适的电平，然后被积分以重新捕获原始的直流和低频信号分量。 积分基本上将经滤波的分量恢复到放大信号中的原始值，使用有界幅度的积分的任意常数来产生恢复的信号。 使用利用预定信号模式或期望信号的固有信号特性的各种技术，可以合理地估计DC偏移。 然后从恢复的信号中减去DC偏移估计，使得放大的接收信号基本上没有失真。 用于区分和数字化接收信号的有利方法使用压缩增量调制技术。

    Phasenvergleichsschaltung
    79.
    发明公开
    Phasenvergleichsschaltung 失效
    相位比较器电路

    公开(公告)号：EP0414305A3

    公开(公告)日：1991-10-23

    申请号：EP90202200.3

    申请日：1990-08-15

    申请人： Philips Patentverwaltung GmbH ,  Philips Electronics N.V.

    发明人： Janta, Dieter ,  Jansen, Winfried

    IPC分类号： H03D13/00

    CPC分类号： H03D13/008 ,  H03D7/14 ,  H03D2200/0009 ,  H03D2200/0033 ,  H03D2200/0047

    摘要： Bei einer Phasenvergleichsschaltung mit einer Doppelgegen­takt-Mischstufe, der ein Sinsussignal sowie dieses Sinus­signal in Gegenphase und ein Rechteck-Schaltsignal gleicher Sollfrequenz zugeführt sind, ist vorgesehen, daß zwei aktive Stromspiegelschaltungen eingesetzt sind, in denen wenigstens zwei gemeinsame Gegenkopplungsschaltungs­elemente vorgesehen sind, von denen das erste in der eingangsseitigen Gegenkopplung der ersten Stromspiegel­schaltung und in der ausgangsseitigen Gegenkopplung der zweiten Stromspiegelschaltung und das zweite in umge­kehrter Weise wirksam ist. Die beiden Stromspiegelschal­tungen werden mittels einer Schaltstufe wechselweise im Halbperioden-Takt des Schaltsignals an die beiden Gegentakt-Mischstufen geschaltet.

    Phasenvergleichsschaltung
    80.
    发明公开
    Phasenvergleichsschaltung 失效
    相比较。

    公开(公告)号：EP0414305A2

    公开(公告)日：1991-02-27

    申请号：EP90202200.3

    申请日：1990-08-15

    申请人： Philips Patentverwaltung GmbH ,  Philips Electronics N.V.

    发明人： Janta, Dieter ,  Jansen, Winfried

    IPC分类号： H03D13/00

    CPC分类号： H03D13/008 ,  H03D7/14 ,  H03D2200/0009 ,  H03D2200/0033 ,  H03D2200/0047

    摘要： Bei einer Phasenvergleichsschaltung mit einer Doppelgegen­takt-Mischstufe, der ein Sinsussignal sowie dieses Sinus­signal in Gegenphase und ein Rechteck-Schaltsignal gleicher Sollfrequenz zugeführt sind, ist vorgesehen, daß zwei aktive Stromspiegelschaltungen eingesetzt sind, in denen wenigstens zwei gemeinsame Gegenkopplungsschaltungs­elemente vorgesehen sind, von denen das erste in der eingangsseitigen Gegenkopplung der ersten Stromspiegel­schaltung und in der ausgangsseitigen Gegenkopplung der zweiten Stromspiegelschaltung und das zweite in umge­kehrter Weise wirksam ist. Die beiden Stromspiegelschal­tungen werden mittels einer Schaltstufe wechselweise im Halbperioden-Takt des Schaltsignals an die beiden Gegentakt-Mischstufen geschaltet.

    摘要翻译： 在相位比较电路，其包括具有Sinsussignal和反相位此正弦信号和方波的开关信号被提供给相同的标称频率的双平衡混频器，它被提供了用于在其中设置的至少其中第一个两个共用负反馈电路元件中的两个有源电流镜像电路 在第一电流镜电路的输入侧的负反馈，并在第二电流镜电路的输出侧的负反馈，第二个是有效以相反的方式。 两个电流镜电路由开关级的装置交替地在所述开关信号的半个周期时钟连接到所述两个平衡混频器级。