公开(公告)号：EP2131523A1

公开(公告)日：2009-12-09

申请号：EP08847479.6

申请日：2008-10-28

申请人： Thine Electronics, Inc.

发明人： OZAWA, Seiichi

IPC分类号： H04L7/033 ,  H04L25/03

CPC分类号： H04L7/033 ,  H04L7/0083 ,  H04L7/0087 ,  H04L25/03012

摘要： A clock data restoration device 1, which restores a clock signal and data on the basis of an inputted digital signal, comprises an equalizer 10, a sampler 20, a clock generator 30, an equalizer controller 40, and a phase monitor 50. A clock signal CK or CKX as a clock signal restored on the basis of the input digital signal is generated through loop processing by the sampler 20 and the clock generator 30. The level adjustment amount of a high frequency component of the digital signal by the equalizer 10 is controlled through loop processing by the equalizer 10, the sampler 20 and the equalizer controller 40.

摘要翻译： 基于输入的数字信号恢复时钟信号和数据的时钟数据恢复装置1包括均衡器10，采样器20，时钟发生器30，均衡器控制器40和相位监视器50.时钟 基于输入数字信号恢复的时钟信号的信号CK或CKX通过采样器20和时钟发生器30的环路处理产生。均衡器10的数字信号的高频分量的电平调整量为 通过均衡器10，采样器20和均衡器控制器40的环路处理进行控制。

公开(公告)号：EP1564884A4

公开(公告)日：2006-01-18

申请号：EP03770036

申请日：2003-10-30

申请人： THINE ELECTRONICS INC

发明人： OKAMURA JUN-ICHI

IPC分类号： H03K19/0175 ,  H03F3/30 ,  H03F3/45 ,  H03F3/68 ,  H03K19/0948

CPC分类号： H03F3/3028 ,  H03F3/3064 ,  H03F3/4521

摘要： Additionally provided are first and second current-supply circuits (51, 52) for introducing constant currents through load resistors (103, 113, 104, 114) if the common-mode voltage at the input stage exceeds the operating ranges of N-channel/P-channel differential amplifier circuits (1, 2). Such a circuit structure can be an equivalent circuit equivalent to structures where a constant current biased P-channel MOS transistor is connected as a load element to an N-channel of a complementary source-follower circuit (15) at the output stage.

摘要翻译： 当输入电路的共模电压超过N的工作范围的1/2时，添加第一和第二电流供应电路51和52以向负载电阻103,104,113和104引入恒定电流 通道/ P沟道差分放大器电路。 因此，即使在上述情况下，也可以通过将输出电路的互补源极跟随器电路15中的N沟道MOS晶体管连接到恒定电流偏置P沟道MOS晶体管的结构来实现等效电路 作为负载元件。

公开(公告)号：EP1465343A1

公开(公告)日：2004-10-06

申请号：EP01274914.9

申请日：2001-12-07

申请人： Thine Electronics, Inc.

发明人： Omote, Kazuyuki, Thine Eelectronics, Inc.

IPC分类号： H03K19/00

CPC分类号： H04L25/028 ,  H04L25/0272

摘要： A semiconductor integrated circuit capable of stabilizing the amplitude and the offset potential of the output signals without increasing the number of operational amplifiers in a line driver for outputting small-amplitude differential signals to external. The semiconductor integrated circuit includes an output circuit including plural transistors supplied with differential signals, for performing switching operation; a first transistor connected between a firstpower supply potential and the output circuit; a second transistor connected between the output circuit and a second power supply potential; a third transistor connected to the first power supply potential; a fourth transistor forming a current mirror circuit together with the second transistor to flow therein a current proportional to that flowing in the second transistor; a first resistance and a second resistance disposed in a path of a current flowing between the third transistor and the fourth transistor; and a differential amplifier for controlling gate potentials of the first and third transistors such that a potential at a connection point between the first resistance and the second resistance approaches a predetermined potential.

摘要翻译： 能够稳定输出信号的振幅和偏移电位的半导体集成电路，而不增加用于将小幅度差分信号输出到外部的线路驱动器中的运算放大器的数量。 半导体集成电路包括：输出电路，包括供给差分信号的多个晶体管，用于进行开关动作; 连接在第一电源电位和输出电路之间的第一晶体管; 连接在所述输出电路和第二电源电位之间的第二晶体管; 连接到第一电源电位的第三晶体管; 第四晶体管与第二晶体管一起形成电流镜电路，以在其中流动与在第二晶体管中流动的电流成比例的电流; 设置在流过第三晶体管和第四晶体管的电流的路径中的第一电阻和第二电阻; 以及用于控制第一和第三晶体管的栅极电位的差分放大器，使得第一电阻和第二电阻之间的连接点处的电位接近预定电位。

公开(公告)号：EP1437830A1

公开(公告)日：2004-07-14

申请号：EP01965575.2

申请日：2001-09-12

申请人： Thine Electronics, Inc.

发明人： OKAMURA, Junichi

IPC分类号： H03K5/15 ,  H03K3/03

CPC分类号： H03K5/1506 ,  H03K3/0322 ,  H03K5/133

摘要： A semiconductor integrated circuit in which, when leading out multiple-phase clock signal wirings from the ring oscillator circuit capable of oscillating at a high frequency, increase in the area of the substrate and deterioration in the clock phase accuracy caused by the non-uniform stray capacitances among the multiple-phase clock signal wirings are prevented. The semiconductor integrated circuit includes: N-stage amplifying circuits connected in a form of a ring to perform oscillating operation, which amplifying circuits are arranged in a semiconductor substrate to be divided into a plurality of rows, wherein in each row an amplifying circuit of "m-1"th stage and an amplifying circuit of "m"th stage are not adjacent to each other, where m is an arbitrary integer number within a range from 2 to N; and a plurality of wirings for respectively leading out a plurality of output signals from the amplifying circuits disposed in one of the plurality of rows.

摘要翻译： 一种半导体集成电路，其中当从能够以高频率振荡的环形振荡器电路引出多相时钟信号线时，基板的面积增加并且由非均匀杂散引起的时钟相位精度的劣化 防止多相时钟信号线之中的电容。 该半导体集成电路包括：以环的形式连接以执行振荡操作的N级放大电路，该放大电路被布置在半导体衬底中以被分成多行，其中在每行中的放大电路“ 第m级放大电路与第m级放大电路不相邻，其中m是从2到N的范围内的任意整数; 以及多个布线，用于分别引出来自布置在多个行中的一行中的放大电路的多个输出信号。