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    Video signal receiption device and video signal transmission system
    5.
    发明授权
    Video signal receiption device and video signal transmission system 有权
    视频信号接收装置以及视频信号传送系统

    公开(公告)号：EP2421262B1

    公开(公告)日：2013-06-05

    申请号：EP11184046.8

    申请日：2008-10-31

    申请人： Thine Electronics, Inc.

    发明人： OZAWA, Seiichi

    IPC分类号： H04L12/54 ,  G06F3/14 ,  G09G5/00 ,  H04N7/173

    CPC分类号： H04N21/4408 ,  G06F3/14 ,  G09G3/2092 ,  G09G5/006 ,  G09G5/008 ,  G09G2370/10 ,  H04N21/4122 ,  H04N21/43632 ,  H04N21/4405

    摘要： A video transmission device 10 has: a packer 11 which receives a video signal, a sync signal, and a data-enable signal, and generates a plurality of packet signals by packetizing the video signal and the sync signal based on the data-enable signal and according to the number of bytes of a packet corresponding to the number of gradation bits of the video signal; an encode unit 15 which generates a plurality of encoded packet signals by encoding the plurality of packet signals; and a serializer 14 which generates a serial packet signal by parallel-serial converting the plurality of encoded packet signals. The packer 11 generates a control signal including a pulse with a pulse width corresponding to the number of bytes of the packet, and the encode unit 15 subjects a portion of the packet signals corresponding to the pulse in the control signal from the packer, to an encode process which is different from a process for the other portion.

    POWER-ON RESET CIRCUIT
    6.
    发明公开
    POWER-ON RESET CIRCUIT 审中-公开
    BETRIEBS-RESETSCHALTUNG

    公开(公告)号：EP2408111A1

    公开(公告)日：2012-01-18

    申请号：EP10750685.9

    申请日：2010-02-25

    申请人： Thine Electronics, Inc.

    发明人： SUZUKI Hajime ,  MIURA Satoshi

    IPC分类号： H03K17/22 ,  G06F1/24

    摘要： When the value of a power supply voltage (VDD) becomes a first threshold value or higher, a first start-up circuit (20) causes a band gap reference circuit (10) to start a stable operation and a first voltage value (V A ) is output from the band gap reference circuit (10). When the value of the power supply voltage becomes a second threshold value or higher which is greater than the first threshold, a second start-up circuit (40) turns on a PMOS transistor (MP 3 ) of a voltage dividing circuit (30), and a second voltage value (V B ) output from the voltage dividing circuit (30) becomes a value, which is derived by dividing the value of the power supply voltage according to the resistance ratio of resistors (R 31 , R 32 ). From a voltage comparison circuit (50), a reset level voltage value is output when the second voltage value (V B ) is smaller than the first voltage value (V A ), and a power-supply voltage level voltage value is output if the second voltage value (V B ) becomes the first voltage value (V A ) or higher,.

    摘要翻译： 当电源电压（VDD）的值成为第一阈值以上时，第一启动电路（20）使带隙基准电路（10）开始稳定动作，第一电压值（VA） 从带隙参考电路（10）输出。 当电源电压的值成为大于第一阈值的第二阈值以上时，第二启动电路（40）导通分压电路（30）的PMOS晶体管（MP 3）， 并且从分压电路（30）输出的第二电压值（VB）成为通过根据电阻器（R 31，R 32）的电阻比除以电源电压值而导出的值。 从电压比较电路（50），当第二电压值（VB）小于第一电压值（VA）时，输出复位电平电压值，如果第二电压值 值（VB）成为第一电压值（VA）以上。

    TRANSMITTING APPARATUS, RECEIVING APPARATUS, TRANSMITTING/RECEIVING SYSTEM, AND IMAGE DISPLAY SYSTEM
    7.
    发明公开
    TRANSMITTING APPARATUS, RECEIVING APPARATUS, TRANSMITTING/RECEIVING SYSTEM, AND IMAGE DISPLAY SYSTEM 审中-公开
    SENDEVORRICHTUNG，EMPFANGSVORRICHTUNG，SENDE- UND EMPFANGSSYSTEM UND BILDANZEIGESYSTEM

    公开(公告)号：EP2393234A1

    公开(公告)日：2011-12-07

    申请号：EP10826588.5

    申请日：2010-10-20

    申请人： Thine Electronics, Inc.

    发明人： OZAWA Seiichi ,  AKITA Hironobu

    IPC分类号： H04L7/00 ,  H04L7/04

    CPC分类号： H04L7/10 ,  G09G3/2096 ,  G09G3/3611 ,  G09G2370/08 ,  G09G2370/14 ,  H04L7/0008 ,  H04L7/0091 ,  H04L7/0337

    摘要： A data reception unit 21 of a reception device 20 n receives calibration data to detect a data reception state or a clock reception state in the reception device 20 n from a data transmission unit 11 of a transmission device 10. A decoder unit 24 causes a transmission unit 26 to send out calibration sample data that a sampler unit 23 obtained by sampling calibration data to the transmission device 10. A control unit 15 of the transmission device 10 detects a data reception state or a clock reception state in the reception device 20 n based on calibration sample data received from the reception device 20 n and controls the data transmission unit 11 and a clock transmission unit 12 based on the detection result.

    摘要翻译： 接收装置20 n的数据接收单元21从发送装置10的数据发送单元11接收校准数据以检测接收装置20 n中的数据接收状态或时钟接收状态。解码器单元24进行发送 单元26发送校准样本数据，该采样器单元23通过采样校准数据获得的采样器单元23发送到发送设备10.发送设备10的控制单元15在接收设备20 n中检测数据接收状态或时钟接收状态 根据从接收装置20 n接收到的校准样本数据，并根据检测结果控制数据发送单元11和时钟发送单元12。

    PLL FREQUENCY SYNTHESIZER
    9.
    发明公开
    PLL FREQUENCY SYNTHESIZER 审中-公开
    PLL-FREQUENZ合成器

    公开(公告)号：EP2124342A1

    公开(公告)日：2009-11-25

    申请号：EP08711039.1

    申请日：2008-02-08

    申请人： Thine Electronics, Inc.

    发明人： SUGANO, Takayuki ,  YATSUDA, Senichiro ,  OHTSUKA, Shigeki ,  CHIBA, Yutaka

    IPC分类号： H03L7/107 ,  H03L7/093

    CPC分类号： H03L7/093 ,  H03L7/0891 ,  H03L7/107 ,  H03L7/1075 ,  H03L7/183

    摘要： A PLL frequency synthesizer 1 according to one embodiment of the present invention is provided with a frequency divider 30, a phase comparator 40, a charge pump 50, a loop filter 60, a voltage controlled oscillator 70, and a changeover switch (within the switching unit 80). The loop filter 60 has a reference potential on a semiconductor substrate as a ground potential, and the changeover switch is formed on the semiconductor substrate 2 and switches connection between an intermediate node of the loop filter 60 and the reference potential on the semiconductor substrate 2 to switch the time constant of the loop filter 60.

    摘要翻译： 根据本发明的一个实施例的PLL频率合成器1具有分频器30，相位比较器40，电荷泵50，环路滤波器60，压控振荡器70和转换开关（在开关 单位80）。 环路滤波器60在半导体衬底上具有作为接地电位的参考电位，并且转换开关形成在半导体衬底2上，并且将环路滤波器60的中间节点与半导体衬底2上的参考电位之间的连接切换到 切换环路滤波器60的时间常数。

    CLOCK DATA RESTORING DEVICE
    10.
    发明公开
    CLOCK DATA RESTORING DEVICE 有权
    TAKTDATEN-WIEDERHERSTELLUNGSVORRICHTUNG

    公开(公告)号：EP2075949A1

    公开(公告)日：2009-07-01

    申请号：EP07806838.4

    申请日：2007-09-06

    申请人： Thine Electronics, Inc.

    发明人： OZAWA, Seiichi

    IPC分类号： H04L7/033 ,  H03L7/00 ,  H04B3/06 ,  H04L25/03

    CPC分类号： H04L7/033 ,  H03L7/091 ,  H04L7/0083 ,  H04L7/0087 ,  H04L25/03057

    摘要： The clock data restoration device 1 is a device which restores a clock signal and data on the basis of an input digital signal and comprises an equalizer section 10, a sampler section 20, a clock generation section 30, an equalizer control section 40, and a phase monitor section 50. As a result of the loop processing of the equalizer section 10, the sampler section 20, and the equalizer control section 40, a control of a level adjustment amount of the digital signal by the equalizer section 10 is carried out However, the control is stopped by the phase monitor section 50 when the phase difference between the clock signal CK and the digital signal is greater than a predetermined value. As a result, a clock signal and data can be restored more accurately.

    摘要翻译： 时钟数据恢复装置1是基于输入数字信号恢复时钟信号和数据的装置，包括均衡器部分10，采样器部分20，时钟产生部分30，均衡器控制部分40和 作为均衡器部分10，采样器部分20和均衡器控制部分40的环路处理的结果，执行了均衡部分10对数字信号的电平调节量的控制。然而， 当时钟信号CK和数字信号之间的相位差大于预定值时，相位监视部件50停止控制。 因此，可以更准确地恢复时钟信号和数据。