Direct wind coil winding head assembly
    2.
    发明公开
    Direct wind coil winding head assembly 失效
    Wickelkopfes zum direktem Wicklen。

    公开(公告)号:EP0674328A1

    公开(公告)日:1995-09-27

    申请号:EP95104327.2

    申请日:1995-03-23

    IPC分类号: H01F41/06 H01F6/06

    摘要: A direct wind coil winding head assembly for depositing coil windings directly onto a coil support mandrel, comprising wire feed means having an input and an output, the wire feed means adapted to receive a continuous length of wire at the input and to cause the wire to exit the output at a first rate, mandrel positioning means for dynamically positioning the coil support mandrel beneath the output and control means coupled to the wire feed means and the mandrel positioning means, the control means operable to cause the mandrel positioning means to dynamically position the coil support mandrel beneath the output such that the exiting wire is deposited onto the mandrel in a predetermined pattern, and further operable to control the wire feed means such that the first rate is substantially equal to a second rate of movement of the coil support mandrel relative to the output, whereby the wire is deposited onto the coil support mandrel with substantially no residual winding stresses. Other systems, devices and methods are disclosed.

    摘要翻译: 一种用于将线圈绕组直接放置到线圈支撑心轴上的直接风线圈绕组头组件,包括具有输入和输出的线馈送装置,所述线馈送装置适于在输入处接收连续长度的线,并且使线 以第一速率离开输出;心轴定位装置,用于将线圈支撑心轴动态地定位在输出下方,并且控制装置联接到送丝装置和心轴定位装置,所述控制装置可操作以使心轴定位装置动态地定位 线圈支撑心轴在输出下方,使得离开的线以预定图案沉积到心轴上,并且还可操作以控制线材馈送装置,使得第一速率基本上等于线圈支撑心轴相对的第二速率 到输出端,由此线基本上没有残余的缠绕应力沉积到线圈支撑心轴上。 公开了其他系统,装置和方法。

    Switch for serial or parallel communication networks
    3.
    发明公开
    Switch for serial or parallel communication networks 失效
    Schalterfürserielle oder parallele Kommunikationsnetzwerken。

    公开(公告)号:EP0573736A2

    公开(公告)日:1993-12-15

    申请号:EP93101940.0

    申请日:1993-02-08

    IPC分类号: G06F15/16

    CPC分类号: G06F15/17375 G06F15/17343

    摘要: A communication switch apparatus and a method for use in a geographically extensive serial, parallel or hybrid communication network linking a multi-processor or parallel processing system has a very low software processing overhead in order to accommodate random burst of high density data. Associated with each processor is a communication switch. A data source and a data destination, a sensor suite or robot for example, may also be associated with a switch. The configuration of the switches in the network are coordinated through a master processor node and depends on the operational phase of the multi-processor network: data acquisition, data processing, and data exchange. The master processor node passes information on the state to be assumed by each switch to the processor node associated with the switch. The processor node then operates a series of multi-state switches internal to each communication switch. The communication switch does not parse and interpret communication protocol and message routing information. During a data acquisition phase, the communication switch couples sensors producing data to the processor node associated with the switch, to a downlink destination on the communications network, or to both. It also may couple an uplink data source to its processor node. During the data exchange phase, the switch couples its processor node or an uplink data source to a downlink destination (which may include a processor node or a robot), or couples an uplink source to its processor node and its processor node to a downlink destination.

    摘要翻译: 用于连接多处理器或并行处理系统的地理上广泛的串行,并行或混合通信网络中的通信交换设备和方法具有非常低的软件处理开销,以适应高密度数据的随机突发。 与每个处理器相关联的是一个通讯开关。 数据源和数据目的地,例如传感器套件或机器人也可以与开关相关联。 网络中的交换机的配置通过主处理器节点进行协调,并且取决于多处理器网络的操作阶段:数据采集,数据处理和数据交换。 主处理器节点将关于每个交换机假设的状态的信息传递给与交换机相关联的处理器节点。 然后,处理器节点在每个通信交换机内部操作一系列多状态交换机。 通信交换机不解析和解释通信协议和消息路由信息。 在数据采集阶段期间,通信交换机将产生数据的传感器与与交换机相关联的处理器节点耦合到通信网络上的下行链路目的地,或耦合到两者。 它也可以将上行链路数据源耦合到其处理器节点。 在数据交换阶段期间,交换机将其处理器节点或上行链路数据源耦合到下行链路目的地(其可以包括处理器节点或机器人),或将上行链路源耦合到其处理器节点及其处理器节点到下行链路目的地 。

    Parallel data transfer network controlled by a dynamically reconfigurable serial network
    4.
    发明公开
    Parallel data transfer network controlled by a dynamically reconfigurable serial network 失效
    通过动态地重新配置的串行网络控制的并行数据传输网络。

    公开(公告)号:EP0562251A2

    公开(公告)日:1993-09-29

    申请号:EP93101935.0

    申请日:1993-02-08

    IPC分类号: G06F15/16

    CPC分类号: G06F15/17368

    摘要: The present device provides for dynamically configurable communication network having a multi-processor parallel processing system having a serial communication network and a high speed parallel communication network. The serial communication network is used to disseminate commands from a master processor (100) to a plurality of slave processors (200) to effect communication protocol, to control transmission of high density data among nodes and to monitor each slave processor's status. The high speed parallel processing network is used to effect the transmission of high density data among nodes in the parallel processing system. Each node comprises a transputer (104), a digital signal processor (114), a parallel transfer controller (106), and two three-port memory devices. A communication switch (108) within each node (100) connects it to a fast parallel hardware channel (70) through which all high density data arrives or leaves the node.

    摘要翻译: 本发明的装置提供用于动态配置通信网络具有具有串行通信网络和一个高速并行通信网络中的多处理器并行处理系统。 串行通信网络被用于传播从主处理器(100),以从处理器(200)的多个命令,以实现通信协议,以控制节点之间的高密度数据的发送和监视的每个从属处理器的状态。 高速并行处理网络被用于实现在并行处理系统中节点之间的高密度数据的传输,每个节点包括一个晶片(104),数字信号处理器(114),并行传送控制器(106),和 两个三端口存储器装置。 每个节点(100)内的通信交换机(108)把它连接到通过其所有高密度数据到达或离开节点的几乎平行的硬件信道(70)。

    Switch for serial or parallel communication networks
    5.
    发明公开
    Switch for serial or parallel communication networks 失效
    用于串行或并行通信网络的开关

    公开(公告)号:EP0573736A3

    公开(公告)日:1995-08-23

    申请号:EP93101940.0

    申请日:1993-02-08

    IPC分类号: G06F15/16

    CPC分类号: G06F15/17375 G06F15/17343

    摘要: A communication switch apparatus and a method for use in a geographically extensive serial, parallel or hybrid communication network linking a multi-processor or parallel processing system has a very low software processing overhead in order to accommodate random burst of high density data. Associated with each processor is a communication switch. A data source and a data destination, a sensor suite or robot for example, may also be associated with a switch. The configuration of the switches in the network are coordinated through a master processor node and depends on the operational phase of the multi-processor network: data acquisition, data processing, and data exchange. The master processor node passes information on the state to be assumed by each switch to the processor node associated with the switch. The processor node then operates a series of multi-state switches internal to each communication switch. The communication switch does not parse and interpret communication protocol and message routing information. During a data acquisition phase, the communication switch couples sensors producing data to the processor node associated with the switch, to a downlink destination on the communications network, or to both. It also may couple an uplink data source to its processor node. During the data exchange phase, the switch couples its processor node or an uplink data source to a downlink destination (which may include a processor node or a robot), or couples an uplink source to its processor node and its processor node to a downlink destination.

    Three dimensional flow processor
    6.
    发明公开
    Three dimensional flow processor 失效
    Dreidimensional Flussprozessor。

    公开(公告)号:EP0610938A1

    公开(公告)日:1994-08-17

    申请号:EP94102081.0

    申请日:1994-02-10

    IPC分类号: G06F15/80 G06F15/16

    CPC分类号: G06F15/803

    摘要: In accordance with the present invention, a three dimensional flow processor (600) is disclosed, comprising a central processing unit (602-610), a first plurality of buses (A', B', C') coupled to the central processing unit, an input data port (634) coupled to at least one of the first plurality of buses and an output data port (628) coupled to at least one of the first plurality of buses, wherein data appearing on the input data port is routed to the output data port if the central processing unit is busy. Other systems, devices and methods are disclosed.

    摘要翻译: 根据本发明,公开了一种三维流处理器(600),其包括中央处理单元(602-610),耦合到中央处理单元的第一多个总线(A',B',C') ,耦合到所述第一多个总线中的至少一个总线的输入数据端口(634)和耦合到所述第一多个总线中的至少一个总线的输出数据端口(628),其中出现在所述输入数据端口上的数据被路由到 输出数据端口,如果中央处理单元正忙。 公开了其他系统,装置和方法。

    Parallel data transfer network controlled by a dynamically reconfigurable serial network
    9.
    发明公开
    Parallel data transfer network controlled by a dynamically reconfigurable serial network 失效
    并行数据传输网络由动态可重构串行网络控制

    公开(公告)号:EP0562251A3

    公开(公告)日:1995-02-01

    申请号:EP93101935.0

    申请日:1993-02-08

    IPC分类号: G06F15/16

    CPC分类号: G06F15/17368

    摘要: The present device provides for dynamically configurable communication network having a multi-processor parallel processing system having a serial communication network and a high speed parallel communication network. The serial communication network is used to disseminate commands from a master processor (100) to a plurality of slave processors (200) to effect communication protocol, to control transmission of high density data among nodes and to monitor each slave processor's status. The high speed parallel processing network is used to effect the transmission of high density data among nodes in the parallel processing system. Each node comprises a transputer (104), a digital signal processor (114), a parallel transfer controller (106), and two three-port memory devices. A communication switch (108) within each node (100) connects it to a fast parallel hardware channel (70) through which all high density data arrives or leaves the node.

    摘要翻译: 本装置提供具有多处理器并行处理系统的动态可配置通信网络,所述多处理器并行处理系统具有串行通信网络和高速并行通信网络。 串行通信网络用于将来自主处理器(100)的命令传播到多个从处理器(200)以实现通信协议,控制节点间高密度数据的传输并监视每个从处理器的状态。 高速并行处理网络用于实现并行处理系统中节点间高密度数据的传输。 每个节点包括一个计算机(104),一个数字信号处理器(114),一个并行传输控制器(106)和两个三端口存储器装置。 每个节点(100)内的通信交换机(108)将其连接到所有高密度数据到达或离开节点的快速并行硬件通道(70)。

    Cryogenic support system
    10.
    发明公开
    Cryogenic support system 失效
    Tieftemperaturhalterungssystem。

    公开(公告)号:EP0294639A2

    公开(公告)日:1988-12-14

    申请号:EP88108203.6

    申请日:1988-05-21

    IPC分类号: G12B7/00 F16M11/04 F16S3/00

    摘要: A support system is disclosed for restraining large masses (1) at very low or cryogenic temperatures. The support system employs a tie bar (68) that is pivotally connected at opposite ends to an anchoring support member (62c) and a sliding support member (62d). The tie bar (68) extends substantially parallel to the longitudinal axis of the cold mass assembly (12), and comprises a rod (102) that lengthens when cooled and a pair of end attachments that contract when cooled. The rod and end attachments are sized so that when the tie bar is cooled to cryogenic temperature, the net change in tie bar length is approximately zero. Longitudinal force directed against the cold mass assembly is distributed by the tie bar between the anchoring support member (62c) and the sliding support member (62d).

    摘要翻译: 公开了用于在非常低或低温下抑制大质量(1)的支撑系统。 支撑系统采用在相对端枢转地连接到锚固支撑构件(62c)和滑动支撑构件(62d)的连杆(68)。 连接杆(68)基本上平行于冷质量组件(12)的纵向轴线延伸,并且包括当冷却时延长的杆(102)和在冷却时收缩的一对末端附件。 杆和端部附件的尺寸使得当连杆被冷却到低温时,连杆长度的净变化大约为零。 针对冷质量组件的纵向力由锚杆在锚定支撑构件(62c)和滑动支撑构件(62d)之间分配。