Multi channel imaging engine apparatus
    1.
    发明公开
    Multi channel imaging engine apparatus 审中-公开
    Mehrkanal-Abbildungs引擎

    公开(公告)号:EP1615450A2

    公开(公告)日:2006-01-11

    申请号:EP05020759.6

    申请日:2001-01-17

    IPC分类号: H04N9/31 H04N5/74

    摘要: A multi channel video engine (10) for accepting, dividing, modifying and recombining light to project an image. A housing (12) encloses an optical assembly (28) having a dichroic mirror assembly (58) and a color cube (60). A plurality of LCD assemblies (30) accept light from the dichroic mirror assembly (58), modifies it, and reflects it to the color cube (60). A lens assembly (16) is affixed to a bulkhead (24) of the housing (12) using a lens cradle (14) and lens retainer (18). An output prism (54) aligns light onto a second plane (70) to coincide with an optical axis (72) of the lens assembly (16).

    摘要翻译: 一种用于接收,分割,修改和重新组合光以投射图像的多通道视频引擎(10)。 壳体(12)包围具有分色镜组件(58)和彩色立方体(60)的光学组件(28)。 多个LCD组件(30)接受来自分色镜组件(58)的光,对其进行修改,并将其反射到彩色立方体(60)。 透镜组件(16)使用透镜支架(14)和透镜保持器(18)固定到壳体(12)的隔板(24)。 输出棱镜(54)将光对准到第二平面(70)以与透镜组件(16)的光轴(72)重合。

    MULTI CHANNEL IMAGING ENGINE APPARATUS
    2.
    发明公开
    MULTI CHANNEL IMAGING ENGINE APPARATUS 有权
    多路图像引擎

    公开(公告)号:EP1262059A1

    公开(公告)日:2002-12-04

    申请号:EP01942830.9

    申请日:2001-01-17

    IPC分类号: H04N3/04 H04N3/22 H04N5/64

    摘要: A multi channel video engine (10) for accepting, dividing, modifying and recombining light to project an image. A housing (12) encloses an optical assembly (28) having a dichroic mirror assembly (58) and a color cube (60). A plurality of LCD assemblies (30) accept light from the dichroic mirror assembly (58), modifies it, and reflects it to the color cube (60). A lens assembly (16) is affixed to a bulkhead (24) of the housing (12) using a lens cradle (14) and lens retainer (18). An output prism (54) aligns light onto a second plane (70) to coincide with an optical axis (72) of the lens assembly (16).

    PLANAR REFLECTIVE LIGHT VALVE BACKPLANE AND METHOD FOR MANUFACTURING THE SAME
    3.
    发明公开
    PLANAR REFLECTIVE LIGHT VALVE BACKPLANE AND METHOD FOR MANUFACTURING THE SAME 有权
    对于A光阀的平反射BACK和方法

    公开(公告)号:EP1152886A1

    公开(公告)日:2001-11-14

    申请号:EP99967562.2

    申请日:1999-12-23

    IPC分类号: B32B3/10

    摘要: A planar wafer based device (e.g., a reflective light valve backplane) is shown in the Figure and includes a substrate having a plurality of surface projections (e.g., pixel mirrors) defining gaps therebetween, an etch-resistant layer formed on the substrate, and a fill layer formed on a portion of the etch-resistant layer in the gaps. A method for manufacturing the planar reflective light valve backplane includes the steps of providing a substrate (e.g., a reflective backplane) including a plurailty of surface projections (e.g., pixel mirrors) defining gaps therebetween, forming an etch-resistant layer on the substrate and a fill layer on the etch resistant layer, etching the fill layer to expose portions of the etch-resistant layer overlying the projections, leaving a portion of the fill layer in the gaps, and optionally forming a protective layer over the exposed portions of the etch-resistant and the fill layers.

    SYSTEM AND METHOD FOR USING COMPOUND DATA WORDS TO REDUCE THE DATA PHASE DIFFERENCE BETWEEN ADJACENT PIXEL ELECTRODES
    6.
    发明公开
    SYSTEM AND METHOD FOR USING COMPOUND DATA WORDS TO REDUCE THE DATA PHASE DIFFERENCE BETWEEN ADJACENT PIXEL ELECTRODES 审中-公开
    系统和方法来使用数据组的话数据相位差与相邻的像素电极为了减少

    公开(公告)号:EP1057166A1

    公开(公告)日:2000-12-06

    申请号:EP99936139.7

    申请日:1999-02-22

    IPC分类号: G09G3/20

    摘要: A system (900) and method (1500) for reducing the phase difference between adjacent gray scale values employ compound data words (504). The compound data words (504) include a first group of data bits (EB3-EB1) and a second group of data bits (B5-B0). A display driver circuit (900) is configured to provide display control signals causing each bit of the first group of data bits (EB3-EB1) to be asserted on the display pixel for a coequal time period, and causing each bit of the second group of data bits (B5-B0) to be asserted on the display pixel for a time period dependent on an associated significance of each bit. Optionally, the display driver circuit (900) further includes a compound data generator (902) configured to provide the compound data words (504). A method for asserting a compound data word on a display pixel includes the steps of asserting each bit of the first group of bits on the display pixel for a coequal time period, and asserting each bit of the second group of bits on the display pixel for a time period dependent on an associated significance of each bit.

    LIGHT SEPARATION AND RECOMBINATION SYSTEM FOR AN OFF-AXIS PROJECTOR
    8.
    发明授权
    LIGHT SEPARATION AND RECOMBINATION SYSTEM FOR AN OFF-AXIS PROJECTOR 有权
    安排用于离轴PROJECTOR分离和重组的光束的

    公开(公告)号:EP1023625B1

    公开(公告)日:2004-01-07

    申请号:EP98953446.6

    申请日:1998-10-13

    IPC分类号: G02B27/10

    CPC分类号: H04N9/3105

    摘要: A color separation and recombination system separates a beam of white light traveling along an optical axis into three differently colored light beams. The system then independently modulates each colored beam and recombines the colored beams to create a color image. The system includes a crossed pair of dichroic filters to separate the beam of white light and to recombine the modulated bundles. The system also includes a pair of aberration-compensating elements that equalize the optical thickness of glass through which each light bundle passes. This equalization of optical thickness equalizes the aberration induced into each bundle. In another embodiment the beam of white light is polarized before separation. The polarities of the colored light beams are then modulated using a spatial light modulator. An analyzer and half-wave plate are provided between the spatial light modulator and the crossed dichroic filters to pass only a portion of the modulated light. The half-wave plate ensures that the modulated light incident on the crossed dichroic filters is of the same polarity as was the polarized white light separated by the crossed dichroic filters.

    Projection system with an offset lens array to reduce vertical banding
    9.
    发明公开
    Projection system with an offset lens array to reduce vertical banding 审中-公开
    具有偏移柱状透镜的投影系统,以减少垂直带

    公开(公告)号:EP1262812A2

    公开(公告)日:2002-12-04

    申请号:EP02011803.0

    申请日:2002-05-28

    IPC分类号: G02B27/18 G02B27/00 G02B3/00

    摘要: The mechanism of and a solution to the problem of vertical banding in projection systems (100) is disclosed. An offset lens array (306, 308) includes a plurality of lens elements (312, 313) arranged in a plurality of rows that are offset with respect to one another. The offset lens array (306, 308) is incorporated in an illuminator (102) for a projection system (100). The asymmetrical arrangement of the rows of lens elements (312, 313) in the array (306, 308) with respect to a seam (126) in a color separation element (106) of the projection system (100) substantially reduces the vertical banding in the projected image (Fig. 7).

    METHOD FOR MODULATING A MULTIPLEXED PIXEL DISPLAY
    10.
    发明公开
    METHOD FOR MODULATING A MULTIPLEXED PIXEL DISPLAY 有权
    一种用于调节多重像素,显示

    公开(公告)号:EP1093654A1

    公开(公告)日:2001-04-25

    申请号:EP99920403.5

    申请日:1999-05-07

    IPC分类号: G09G3/36

    摘要: A method for displaying multi-bit data words on a display including a plurality of pixel electrodes (612), a plurality of storage elements (702), a first voltage supply terminal (622), a second voltage supply terminal (624), a common electrode (626), and a plurality of multiplexers (704) each selectively coupling an associated one of the pixel electrodes (612) with one of the first voltage supply terminal (622) and the second voltage supply terminal (624) responsive to a value of a data bit stored in an associated one of said storage elements (702), includes the steps of sequentially writing (steps 1004 and 1008) each bit of the multi-bit data words to the storage elements (702), and asserting, while each bit is stored in the storage elements (702), a first predetermined voltage on the first voltage supply terminal (622), a second predetermined voltage on the second voltage supply terminal (624), and a third predetermined voltage on the common electrode (626), for a time dependent on the significance of the stored bit (step 1002).