Abstract:
The invention relates to transceiver comprising a sub-sampling based frequency synthesizer with a sampling frequency f smp , configured to generate M different output signals 3 for use as a carrier signal for transmission and/or a signal with a channel frequency for reception. M is an integer greater than 4, each output signal has a corresponding predefined frequency. The predefined frequencies are within a frequency band with a predefined bandwidth CFR. CFR is greater than f smp . The frequency synthesizer comprises a frequency shift unit configured for shifting a version of the output signal over a predefined frequency shift f shift to obtain a frequency shifted signal which is supplied to a sampling unit of the sub-sampling based frequency synthesizer, wherein -f smp /2 f shift +f smp /2. The frequency shift unit is configured to use for the generation of each of the N different output signals a corresponding predefined frequency shift f shift .
Abstract:
Antenna diversity integrated circuit having two or more RF input connections for connecting an antenna (1a, 1b, 1c). A low noise amplifier circuit is present having a first stage (7a, 7b, 7c) for each one of the two or more RF input connections and a single second stage (8). Output connections of each of the first stages (7a, 7b, 7c) are combined in a single summing node to which an inductor (L) and an input connection of the second stage (8) are connected. During operation one of the two or more first stages (7a, 7b, 7c) is activated to provide an input signal to the second stage (8).
Abstract:
The invention relates to transceiver 1 comprising a frequency synthesizer 2 configured to generate an output signal 3 for use as a carrier signal for transmission and/or a signal with a channel frequency for reception, wherein the frequency synthesizer is a sub-sampling based frequency locked loop frequency synthesizer. The combination of a FLL and sub-sampling allows to obtain a sub-sample based locked loop with a closed loop response similar to a PLL but with improved settling time and improved suppression of high frequency components of the quantization noise due to the sampling process. The invention allows to obtain a frequency synthesizer with improved characteristics with respect to at least one of power consumption, locking characteristic, design optimization characteristics compared to non-sub-sampling PLL based frequency synthesizers.
Abstract:
A receiver and method for determin ing a characteristic from an input signal is disclosed. A characteristic is at least one selected from a group comprising preamble detect, frequency offset and timing offset. The input signal comprises an IF frequency fIF and a preamble signal which is a sequence of M similar data symbols. The data symbols have a symbol period SP, and M is an integer greater than or equal to 2. The method comprises: - receiving N subsequent samples of the input signal, the N subsequent s amples representing a part of the input signal approximating the symbol period SP, - rotating N subsequent samples to obtain N rotated symbols; - correlating the N rotated symbols with P correlation functions to generate a set of N x P correlation values, P being an integer greater than or equal to 2; and, - selecting a maximum correlation value from the set of N x P correlation values and determining the characteristic. The invention enables to perform an efficient antenna diversi ty circuit, which can be u sed for simultaneously timing offset and frequency offset estimation, and preamble detection for both antennae with only one radio unit.
Abstract:
Method for receiving data packet transmissions, wherein synchronization with a transmitter is accomplished based on detection of a preamble transmitted by the transmitter. A time multiplexing scheduling of a single hardware receiver arrangement is used, and the time multiplexing scheduling has a main time slot comprising a first listen period and a second listen period following the first listen period. In the first listen period a first type of synchronization detection is executed (e.g. IEEE 802.15.4), and in the second listen period a second type of synchronization detection different from the first type of synchronization detection is executed (e.g. BLE).