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公开(公告)号：EP1815591A1
公开(公告)日：2007-08-08
申请号：EP05802353.2
申请日：2005-09-07
CPC分类号： H03F3/191 , H03F2200/294 , H03F2200/372 , H03F2200/72
摘要： Tunable low noise amplifier using an RF current feed back loop (L) coupled between input (IM) and output (OM) means and including first (CAI) and second (CA2) serially coupled first order lowpass RF current amplifiers as well RF current inverter means (INV). To obtain narrow bandpass selectivity within a relatively wide tuning range e.g. from 40MHz to 1000MHz said first RF current amplifier is being provided with a current gain larger than that of the second RF current amplifier, and a 3 dB cut off frequency lower than the 3 dB cut off frequency of said second RF current amplifier, a tuning control signal being supplied to both first and second RF current amplifiers to vary the respective 3 dB cut off frequencies thereof.
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公开(公告)号：EP1423910B1
公开(公告)日：2007-01-10
申请号：EP02797945.9
申请日：2002-09-01
IPC分类号： H03D3/00
摘要： Receiver comprising an RF front end circuit for a selection and conversion of an RF input signal into a pair of quadrature IF (intermediate frequency) signals being supplied through in-phase and phase quadrature signal paths to signal inputs of quadrature phase detection means included in a (PLL) phase locked loop, an output of said quadrature phase detection means being coupled through a loop filter to a control input of a quadrature IF oscillator supplying a pair of quadrature IF oscillator signals to carrier inputs of said quadrature phase detection means. To suppress amplitude and phase mismatch deteriorating proper mirror cancellation said quadrature phase detection means is coupled to amplitude and phase error detection means for a detection of amplitude and phase errors in the output signal of said quadrature phase detection means and a quadrature frequency doubler is coupled between the quadrature local oscillator and carrier inputs of said amplitude and phase error detection means to supply respectively thereto in-phase and phase quadrature error detection carrier signals at twice the IF carrier frequency of said pair of quadrature IF signals, said amplitude and phase error detection means respectively providing amplitude and phase error signals through first and second low-pass filters to an amplitude correction circuit and a phase correction circuit preceding at least one of the inputs of said quadrature phase detection means for a negative feedback of said amplitude and phase errors.
摘要翻译： 接收器包括RF前端电路，用于选择RF输入信号并将其转换为一对正交IF（中频）信号，通过同相和正交相位信号路径将其提供给正交相位检测装置的信号输入，正交相位检测装置包括在 （PLL）锁相环，所述正交相位检测装置的输出端通过环路滤波器耦合到正交IF振荡器的控制输入端，将一对正交IF振荡器信号提供给所述正交相位检测装置的载波输入端。 为了抑制恶化适当反射镜消除的幅度和相位失配，所述正交相位检测装置被耦合到幅度和相位误差检测装置，用于检测所述正交相位检测装置的输出信号中的幅度和相位误差，并且正交倍频器被耦合 所述幅度和相位误差检测装置的正交本地振荡器和载波输入端分别向所述一对正交IF信号的两倍IF载波频率提供同相和正交相位误差检测载波信号，所述幅度和相位误差检测装置 分别通过第一和第二低通滤波器将振幅和相位误差信号提供给振幅校正电路和在所述正交相位检测装置的至少一个输入之前的相位校正电路，用于所述振幅和相位误差的负反馈。
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3.发明公开MIRROR SUPPRESSION CIRCUIT IN A QUADRATURE DEMODULATOR 审中-公开EINEM QUADRATUR-DEMODULATOR中的SPIEGELUNTERDRÜCKUNGSSCHALTUNG
公开(公告)号：EP1361655A1
公开(公告)日：2003-11-12
申请号：EP02076835.4
申请日：2002-05-07
IPC分类号： H03D3/00
CPC分类号： H03D3/009
摘要： Mirror suppression circuit and receiver using such mirror suppression circuit comprising a first quadrature signal path coupled between quadrature signal input and output terminals and including an error correction circuit for correction of amplitude and phase errors in a carrier modulated quadrature signal comprising a pair of in-phase and phase quadrature signal components. To obtain a suppression of both amplitude and phase imbalance of said carrier modulated quadrature signal as well as signal amplitude variations, a quadrature output of said error correction circuit being coupled through a first filter circuit for a selection of said quadrature signal to a first quadrature input of an error detection circuit, said first quadrature signal path being coupled prior to said first filter circuit through a second quadrature signal path to a second quadrature input of said error detection circuit, said error detection circuit detecting amplitude and phase errors and providing amplitude and phase control signals to amplitude and phase control inputs of said error correction circuit for a negative feed back of said amplitude and phase errors to said error correction circuit, said amplitude control signal varying with at least one of products I w *I ref and Q w *Q ref and said phase control signal varying with at least one of products I w *Q ref and Q w *I ref , I w and Q w , respectively I ref and Q ref , representing the in-phase and phase quadrature signal components of said quadrature signal at the first quadrature input of the error detection circuit, respectively the in-phase and phase quadrature signal components of a quadrature reference signal occurring at the negative carrier frequency of said quadrature signal at the second quadrature input ofthe error detection circuit.
摘要翻译： 镜像抑制电路和接收机，其使用这种镜像抑制电路，其包括耦合在正交信号输入和输出端之间的第一正交信号路径，并且包括用于校正载波调制正交信号中的幅度和相位误差的纠错电路，该纠错电路包括一对同相 和相位正交信号分量。 为了获得对所述载波调制正交信号的幅度和相位不平衡以及信号幅度变化的抑制，所述误差校正电路的正交输出通过第一滤波器电路耦合，用于选择所述正交信号到第一正交输入 所述第一正交信号路径在所述第一滤波器电路之前通过第二正交信号路径耦合到所述误差检测电路的第二正交输入，所述误差检测电路检测幅度和相位误差并提供幅度和相位 将所述误差校正电路的幅度和相位控制输入的控制信号用于所述幅度和相位误差的负反馈到所述误差校正电路，所述幅度控制信号随着乘积Iw * Iref和Qw * Qref中的至少一个而变化，并且所述 相位控制信号随产品Iw * Qref和Qw * Iref，Iwand Qw，re中的至少一个而变化 分别表示误差检测电路的第一正交输入处的所述正交信号的同相和相位正交信号分量的Iref和Qref，分别是在负载波上发生的正交参考信号的同相和相位正交信号分量 误差检测电路的第二正交输入处的所述正交信号的频率。
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公开(公告)号：EP1251633A1
公开(公告)日：2002-10-23
申请号：EP01201441.1
申请日：2001-04-20
IPC分类号： H03B5/20
CPC分类号： H03B5/20
摘要： Controllable oscillator circuit comprising a regenerative loop which incorporates a cascade circuit of first and second sections each having a controllable gain and a phase shift which is 90° at the oscillation frequency, the first and second sections comprising first and second transconductance amplifiers, respectively, outputs of which are coupled to third and fourth transconductance amplifiers, which are positively fed back from the output to the input, and via first and second capacitors to inputs of the second and first gain controlled amplifiers, said first and second capacitors being coupled in parallel to first and second load resistors, respectively, a tuning control current being supplied to control inputs of the first and second transconductance amplifiers, the output of at least one of the first and second transconductance amplifiers being coupled to an amplitude detection arrangement providing a gain control current for an automatic gain control to control inputs of the third and fourth transconductance amplifiers, said first and third transconductance amplifiers of the first section having a differential pair of first and second output terminals in common, said second and fourth transconductance amplifiers of the second section having a differential pair of third and fourth output terminals in common. In order to provide an oscillator capable of generating sinusoidal signals and tuneable at lower tuning frequencies and operating at lower supply voltages than the above conventional oscillator circuit, said first and second parallel RC filters are coupled between the first and second output terminals and the third and fourth output terminals, respectively, said first to fourth output terminals being respectively coupled to first to fourth DC current paths shunting at least a substantial part of said tuning and gain control currents to a supply voltage.
摘要翻译： 可控振荡器电路包括再生回路，其包括第一和第二部分的级联电路，每个级联电路具有可调增益和在振荡频率下为90°的相移，第一和第二部分分别包括第一和第二跨导放大器，输出 其耦合到第三和第四跨导放大器，其从输出端被正反馈到输入端，并且经由第一和第二电容器到第二和第一增益控制放大器的输入端，所述第一和第二电容器并联耦合到 第一和第二负载电阻器，调谐控制电流被提供给第一和第二跨导放大器的控制输入，第一和第二跨导放大器中的至少一个的输出耦合到提供增益控制电流的幅度检测装置 用于自动增益控制来控制输入 第三和第四跨导放大器，所述第一部分的所述第一和第三跨导放大器具有共同的第一和第二输出端的差分对，所述第二部分的所述第二和第四跨导放大器具有第三和第四输出端的差分对， 共同。 为了提供能够产生正弦信号并能够在较低调谐频率下调谐并且以比上述常规振荡器电路更低的电源电压操作的振荡器，所述第一和第二并联RC滤波器耦合在第一和第二输出端子之间，第三和第二输出端子 第四输出端子，所述第一至第四输出端子分别耦合到第一至第四直流电流路径，将至少大部分所述调谐和增益控制电流分流至电源电压。
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5.发明公开Receiver comprising a digitally controlled capacitor bank 审中-公开Empfängermit einer digital gesteuerten Kondensatorbank
公开(公告)号：EP1182778A1
公开(公告)日：2002-02-27
申请号：EP00202622.7
申请日：2000-07-21
IPC分类号： H03J5/24
CPC分类号： H03J5/246 , H03J2200/10 , H03J2200/36
摘要： Receiver comprising an RF input filter including a digitally controlled capacitor bank (Cb) with n capacitors being controlled by a tuning control signal (Vtune) for varying the tuning frequency of the RF input filter within a tuning range. For an improvement of the receiver in price/performance ratio the n capacitors of the digitally controlled capacitor bank (Cb) are monolithically integrated, whereas the bandwidth of the tuneable RF input filter is being adjusted to the maximum relative spread of said capacitors. A continuous tuning control signal (Vtune) is being supplied through an analogue to digital converter (A/D) to said capacitor bank (Cb) and to a first input of a differential stage (DS), an output of the analogue to digital converter (A/D) being coupled through a digital to analogue converter (D/A) to a second input of a differential stage (DS), an output of the differential stage (DS) being coupled to a control terminal of a variable capacitance diode (D) being arranged in parallel to the digitally controlled capacitor bank (Cb).
摘要翻译： 接收机包括具有数字控制电容器组（Cb）的RF输入滤波器，其中n个电容器由调谐控制信号（Vtune）控制，用于在调谐范围内改变RF输入滤波器的调谐频率。 为了改善接收机的性价比，数字控制电容器组（Cb）的n个电容器是单片集成的，而可调谐RF输入滤波器的带宽被调整到所述电容器的最大相对扩展。 通过模拟数字转换器（A / D）向所述电容器组（Cb）和差分级（DS）的第一输入端提供连续调谐控制信号（Vtune），模数转换器 （A / D）通过数模转换器（D / A）耦合到差分级（DS）的第二输入端，差分级（DS）的输出端耦合到可变电容二极管 （D）与数字控制电容器组（Cb）并联布置。
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6.发明公开A circuit for measuring absolute spread in capacitors implemented in planary technology 审中-公开在平面执行电路，用于测量绝对散射能力
公开(公告)号：EP1158303A1
公开(公告)日：2001-11-28
申请号：EP00201821.6
申请日：2000-05-25
IPC分类号： G01R27/26 , G01R31/316
CPC分类号： G01R31/2884 , G01R27/2605
摘要： A circuit for measuring absolute spread in capacitors implemented in planary technology using a charge pump (CP) supplying a charge current to an internal capacitor (Cint), the voltage across the internal capacitor (Cint) being coupled through a comparator (COM) for comparing said voltage with first and second threshold levels to a bistable multivibrator (BM) for reversing the direction of the charge current to charge the internal capacitor (Cint) when said voltage decreases below the second threshold level and to decharge the internal capacitor (Cint), when said voltage increases above the first threshold level, the charge current being determined by a reference voltage being provided across an external resistor (Rext), said first and second threshold levels defining a voltage range being proportional to the reference voltage, an output signal of the bistable multivibrator being coupled to frequency measuring means (CFM) to compare the repetition frequency thereof with a reference frequency.
摘要翻译： 一种用于使用在内部电容（CINT），跨过内部电容器上的电压（CINT）供给充电电流给电荷泵（CP）测量在planary技术实现的电容器绝对传播电路被通过用于比较的比较器（COM），耦合 与第一和第二阈值电平的双稳态多谐振荡器（BM）用于反转充电电流的方向，当所述电压下降到低于第二阈值水平，并除电内部电容器到内部电容（CINT），所述充电电压（CINT） 当第一阈值电平以上的所述电压的增加，是跨越在外部电阻器（Rext的）提供由基准电压开采的充电电流是确定的，所述第一和第二阈值电平限定的电压范围内正比于参考电压的输出信号 双稳态多谐振荡器被耦合到频率测量装置（CFM）至与参考FRE其比较的重复频率 quency。
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公开(公告)号：EP1070388A1
公开(公告)日：2001-01-24
申请号：EP00905019.6
申请日：2000-02-04
CPC分类号： H03F3/2176 , H03F1/0222
摘要： The invention relates to a communication device including a power amplifier for amplifying a modulated high frequency carrier signal comprising a resonance circuit arranged between resonance circuit input means and antenna means. To improve the power added efficiency of the power amplifier, the resonance circuit input means is provided with an excitation circuit for supplying an excitation signal to the resonance circuit phase and/or frequency coupled with the modulated high frequency carrier signal and having a duty cycle significantly less than 50 %.
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公开(公告)号：EP1380099B1
公开(公告)日：2007-08-29
申请号：EP02732619.8
申请日：2002-04-12
IPC分类号： H03B5/20
CPC分类号： H03B5/20
摘要： Controllable oscillator circuit comprising a regenerative loop which incorporates a cascade circuit of first and second sections each having a controllable gain and a phase shift which is 90° at the oscillation frequency, the first and second sections comprising first and second transconductance amplifiers, respectively, outputs of which are coupled to third and fourth transconductance amplifiers, which are positively fed back from the output to the input, and via first and second capacitors to inputs of the second and first gain controlled amplifiers, said first and second capacitors being coupled in parallel to first and second load resistors, respectively, a tuning control current being supplied to control inputs of the first and second transconductance amplifiers, the output of at least one of the first and second transconductance amplifiers being coupled to an amplitude detection arrangement providing a gain control current for an automatic gain control to control inputs of the third and fourth transconductance amplifiers, said first and third transconductance amplifiers of the first section having a differential pair of first and second output terminals in common, said second and fourth transconductance amplifiers of the second section having a differential pair of third and fourth output terminals in common. In order to provide an oscillator capable of generating sinusoidal signals and tuneable at lower tuning frequencies and operating at lower supply voltages than the above conventional oscillator circuit, said first and second parallel RC filters are coupled between the first and second output terminals and the third and fourth output terminals, respectively, said first to fourth output terminals being respectively coupled to first to fourth DC current paths shunting at least a substantial part of said tuning and gain control currents to a supply voltage.
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公开(公告)号：EP1820267A1
公开(公告)日：2007-08-22
申请号：EP05769963.9
申请日：2005-07-19
CPC分类号： H03F3/45085 , H03F1/0205 , H03F1/3217 , H03F3/3069 , H03F3/3093 , H03F2201/3233
摘要： Controllable operational transconductance power amplifier (controllable power OTA) including an input stage receiving a differential input signal (OVin) and deriving therefrom first (i1) and second (i2) low power current signals being coupled to first (ccs1) and second (ccs2) current controlled output current sources being arranged in class B push pull configuration. To obtain an effective gain control while securing power efficiency and linearity, the overall gain of the power OTA is controlled by varying the gain or transconductance of the input stage (c15) and by the use of means for bi-directionally rectifying said first (i1) and second (io) low power current signals and providing in mutual alternation power amplification of said first (i1) and second (i2) low power current signals into first (I01) and second (Io2) mutually exclusive high power current output signals, which are supplied through a current summer to a current output (I0) of said linear power amplifier.
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公开(公告)号：EP1301990B1
公开(公告)日：2006-11-15
申请号：EP01969452.0
申请日：2001-07-19
IPC分类号： H03J5/24
CPC分类号： H03J5/246 , H03J2200/10 , H03J2200/36
摘要： Receiver comprising an RF input filter including a digitally controlled capacitor bank with n capacitors being controlled by a tuning control signal for varying the tuning frequency of the RF input filter within a tuning range. For an improvement of the receiver in price/performance ratio the n capacitors of the digitally controlled capacitor bank are monolythically integrated, whereas the bandwidth of the tunable RF input filter is being adjusted to the maximum relative spread of said capacitors. A continuous tuning control signal is being supplied through an analogue to digital (AD) converter to said capacitor bank and to a first input of a differential stage, an output of the AD converter being coupled through a digital to analogue (DA) converter to a second input of a differential stage, an output of the differential stage being coupled to a control terminal of a variable capacitance diode being arranged in parallel to the digitally controlled capacitor bank.
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