公开(公告)号：EP0225763A2

公开(公告)日：1987-06-16

申请号：EP86309175.7

申请日：1986-11-25

申请人： ADVANCED MICRO DEVICES, INC.

发明人： Joshi, Sunil ,  Iyer, Venkatraman

IPC分类号： H03M13/00

CPC分类号： H03M13/091

摘要： There is disclosed herein a CRC calculation circuit which can calculate CRC checkbits on 8 bits of raw input data per cycle of a byte clock. The calculation apparatus uses 8 rows of shifting links with the inputs of each row coupled to the data outputs of the preceding row. Each shifting link shifts its input bit one bit position toward the most significant bit, and selected shifting links perform an exclusive-OR operation between their input bits and the output of an input exclusive-OR gate which exclusive-OR's (84) one input bit with one of the bits in the most significant byte of the checksum register (30). A byte wide output bus (8) is used to access the final checkbits from the checksum register (30) by disabling the array of shifting links during the output cycles so that the bytes of CRC data can be shifted into position through the array one byte per each cycle of the byte clock. Preset logic for forcing all logic 1's into the data inputs of the first row of shifting links is provided such the machine can be preset during the first clock cycle of the CRC calculation. Several differenct architectures are disclosed for allowing separate calculation of CRC bits on a header packet and a data packet where the CRC bits on the data packet may be calculated on the data alone or the data plus the header and the CRC bits for the header. Logic for allowing CRC calculation to be performed on all bytes of a message while excluding some selected number of bits in the first byte is also disclosed.

公开(公告)号：EP0290172A2

公开(公告)日：1988-11-09

申请号：EP88303676.6

申请日：1988-04-22

申请人： ADVANCED MICRO DEVICES, INC.

发明人： Iyer, Venkatraman ,  Joshi, Sunil P.

IPC分类号： G06F5/06 ,  G06F5/00

CPC分类号： G06F5/065 ,  G06F5/01 ,  G06F13/4018 ,  G06F2205/067

摘要： There is disclosed herein a FIFO for changing the data path width in transmitting data between two data buses. The FIFO allows the data arriving on the narrower of the two data buses to be assembled in a group of registers with the most significant bit on the extreme right or left of the plurality of registers in which the data is being assembled prior to transmission on the wider of the two data buses. The registers may be optionally loaded from left to right or from right to left. Further, means are disclosed to allows the incoming data to be assembled into a larger word starting at any byte boundary in the word.

摘要翻译： 这里公开了一种用于在两条数据总线之间传输数据的数据路径宽度的FIFO。 FIFO允许将到达两个数据总线较窄的数据组装在一组寄存器中，该组寄存器在多个寄存器的最右侧或左侧的最高有效位，在该寄存器中数据正在组装之前， 两条数据总线更宽。 寄存器可以从左到右或从右到左加载。 此外，公开了允许将输入数据组装成从单词中的任何字节边界开始的更大字的装置。

公开(公告)号：EP0171874A3

公开(公告)日：1988-08-10

申请号：EP85303443

申请日：1985-05-16

申请人： ADVANCED MICRO DEVICES, INC.

发明人： Iyer, Venkatraman ,  Lee, Gil

IPC分类号： G11C19/00 ,  G01R31/28

CPC分类号： G01R31/318385 ,  G01R31/31853 ,  G06F11/26 ,  G06F11/27 ,  G06F11/277 ,  G11C19/00

摘要： An apparatus and process employing an integrated circuit device technology within a linear feedback shift register using a cyclic redundancy check code scheme for validating the device technology under realistic very large scale integrated circuit operating conditions. By deploying two feedback shift registers in a full-duplex mode, the device technology can be subjected to arbitrarily-long, pseudorandom test signal sequences. Also, by checking the registers with variable-phase pulses, representative device delay time information can be obtained.

公开(公告)号：EP0290172A3

公开(公告)日：1991-01-16

申请号：EP88303676.6

申请日：1988-04-22

申请人： ADVANCED MICRO DEVICES, INC.

发明人： Iyer, Venkatraman ,  Joshi, Sunil P.

IPC分类号： G06F5/06 ,  G06F5/00

CPC分类号： G06F5/065 ,  G06F5/01 ,  G06F13/4018 ,  G06F2205/067

摘要： There is disclosed herein a FIFO for changing the data path width in transmitting data between two data buses. The FIFO allows the data arriving on the narrower of the two data buses to be assembled in a group of registers with the most significant bit on the extreme right or left of the plurality of registers in which the data is being assembled prior to transmission on the wider of the two data buses. The registers may be optionally loaded from left to right or from right to left. Further, means are disclosed to allows the incoming data to be assembled into a larger word starting at any byte boundary in the word.

公开(公告)号：EP0225763A3

公开(公告)日：1990-03-14

申请号：EP86309175.7

申请日：1986-11-25

申请人： ADVANCED MICRO DEVICES, INC.

发明人： Joshi, Sunil ,  Iyer, Venkatraman

IPC分类号： H03M13/00

CPC分类号： H03M13/091

摘要： There is disclosed herein a CRC calculation circuit which can calculate CRC checkbits on 8 bits of raw input data per cycle of a byte clock. The calculation apparatus uses 8 rows of shifting links with the inputs of each row coupled to the data outputs of the preceding row. Each shifting link shifts its input bit one bit position toward the most significant bit, and selected shifting links perform an exclusive-OR operation between their input bits and the output of an input exclusive-OR gate which exclusive-OR's (84) one input bit with one of the bits in the most significant byte of the checksum register (30). A byte wide output bus (8) is used to access the final checkbits from the checksum register (30) by disabling the array of shifting links during the output cycles so that the bytes of CRC data can be shifted into position through the array one byte per each cycle of the byte clock. Preset logic for forcing all logic 1's into the data inputs of the first row of shifting links is provided such the machine can be preset during the first clock cycle of the CRC calculation. Several differenct architectures are disclosed for allowing separate calculation of CRC bits on a header packet and a data packet where the CRC bits on the data packet may be calculated on the data alone or the data plus the header and the CRC bits for the header. Logic for allowing CRC calculation to be performed on all bytes of a message while excluding some selected number of bits in the first byte is also disclosed.

公开(公告)号：EP0241129A2

公开(公告)日：1987-10-14

申请号：EP87301850.1

申请日：1987-03-03

申请人： ADVANCED MICRO DEVICES, INC.

发明人： Joshi, Sunil Pradeep ,  Iyer, Venkatraman

IPC分类号： G06F5/06

CPC分类号： G06F5/065 ,  G06F2205/064 ,  G06F2205/066

摘要： There is disclosed herein a RAM buffer controller for managing the address input lines of a RAM buffer to simulate the operation of two FIFO's therein. There is also disclosed apparatus for allowing random access by a node processor in a local area network node using the RAM buffer controller to manage transmit and receive FIFO's to have random access to any address in the address space of the buffer without restriction to FIFO boundaries. There is also disclosed appratus for transmitting packets from said buffer organized into one or two linked lists. Further, there is disclosed apparatus for allowing independent initialization of any of the pointers in the RAm buffer controller which are not currently selected, and for allowing software requests for read or write access by the node processor. Further, there is disclosed apparatus and a method for recording status and length information at the end of a packet instead of in front thereof and for allowing any incoming packet to be flushed without saving status information or to be flushed while saving its status information.

摘要翻译： 这里公开了RAM缓冲器控制器，用于管理RAM缓冲器的地址输入线以模拟其中的两个FIFO的操作。 还公开了一种使用RAM缓冲器控制器允许由局域网节点中的节点处理器进行随机访问的装置，用于管理发送和接收FIFO以对缓冲器的地址空间中的任何地址进行随机访问，而不限制于FIFO边界。 还公开了用于从组织成一个或两个链表的所述缓冲器传送分组的设备。 此外，公开了用于允许RAM缓冲器控制器中当前未选择的任何指针的独立初始化的装置，并且允许由节点处理器进行读取或写入访问的软件请求。 此外，公开了一种用于在分组结束时而不是在其前面记录状态和长度信息的装置和方法，并且用于允许任何输入分组被刷新而不保存状态信息或在保存其状态信息的同时被刷新。

公开(公告)号：EP0230730A2

公开(公告)日：1987-08-05

申请号：EP86309177.3

申请日：1986-11-25

申请人： ADVANCED MICRO DEVICES, INC.

发明人： Joshi, Sunil P. ,  Iyer, Venkatraman

IPC分类号： H03M13/00

CPC分类号： H03M13/091

摘要： There is disclosed herein a CRC calculation circuit which can calculate CRC checkbits on 8 bits of raw input data per cycle of a byte clock. The calculation apparatus uses 8 rows of shifting links with the inputs of each row coupled to the data outputs of the preceding row. Each shifting link shifts its input bit one bit position toward the most significant bit, and selected shifting links perform an exclusive-OR operation (84) between their input bits and the output of an input exclusive-OR gate which exclusive-OR's (84) one input bit with one of the bits in the most significant byte of the checksum register (30). A byte wide output (70) bus is used to access the final checkbits from the checksum register (30) by disabling the array of shifting links during the output cycles so that the bytes of CRC data can be shifted into position through the array one byte per each cycle of the byte clock. Preset logic for forcing all logic 1's into the data inputs of the first row of shifting links is provided such the machine can be preset during the first clock cycles of the CRC calculation. Several differenct architectures are disclosed for allowing separate calculation of CRC bits on a header packet and a data packet where the CRC bits on the data packet may be calculated on the data alone or the data plus the header and the CRC bits for the header. Logic for allowing CRC calculation to be performed on all bytes of a message while excluding some selected number of bits in the first byte is also disclosed.

公开(公告)号：EP0230730B1

公开(公告)日：1993-11-10

申请号：EP86309177.3

申请日：1986-11-25

申请人： ADVANCED MICRO DEVICES, INC.

发明人： Joshi, Sunil P. ,  Iyer, Venkatraman

IPC分类号： H03M13/00

CPC分类号： H03M13/091

公开(公告)号：EP0225763B1

公开(公告)日：1993-11-10

申请号：EP86309175.7

申请日：1986-11-25

申请人： ADVANCED MICRO DEVICES, INC.

发明人： Joshi, Sunil ,  Iyer, Venkatraman

IPC分类号： H03M13/00

CPC分类号： H03M13/091

公开(公告)号：EP0226353A3

公开(公告)日：1990-03-14

申请号：EP86309176.5

申请日：1986-11-25

申请人： ADVANCED MICRO DEVICES, INC.

发明人： Joshi, Sunil P. ,  Iyer, Venkatraman

IPC分类号： H03M13/00

CPC分类号： H03M13/091

摘要： There is disclosed herein a CRC calcualtion circuit which can calculate CRC checkbits on 8 bits of raw input data per cycle of a group clock. The calculation apparatus uses 8 rows of shifting links with the inputs of each row coupled to the data outputs of the preceding row. Each shifting link shifts its input bit one bit position toward the most significant bit, and selected shifting links perform an exclusive-OR operaiton between their input bits and the output of an input exclusive-OR gate which exclusive-OR's (84) one input bit with one of the bits in the most significant group of the checksum register (30). A group wide output (70) bus is used to access the final checkbits from the checksum register (34) by disabling the array of shifting links during the output cycles so that the groups of CRC data can be shifted into position through the array one group per each cycle of the group clock. Preset logic for forcing all logic 1's into the data inputs of the first row of shifting links is provided such the machine can be preset during the first clock cycle of the CRC calculation. Several differenct architectures are disclosed for allowing separate calculation of CRC bits on a header packet and a data packet where the CRC bits on the data packet may be calculated on the data alone or the data plus the header and the CRC bits for the header. Logic for allowing CRC calculation to be performed on all groups of a message while excluding some selected number of bits in the first group is also disclosed.