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公开(公告)号：EP1204989A1
公开(公告)日：2002-05-15
申请号：EP00943317.8
申请日：2000-06-29
IPC分类号： H01L21/8247 , H01L27/115
CPC分类号： H01L27/115 , H01L27/11517 , H01L27/11521 , H01L27/11524
摘要： In one embodiment, the present invention relates to a method of forming a NAND type flash memory device, involving the steps of growing a first oxide layer over at least a portion of a substrate, the substrate including a flash memory cell area and a select gate area; removing a portion of the first oxide layer in the flash memory cell area of the substrate; growing a second oxide layer over at least a portion of the substrate in the flash memory cell area and over at least a portion of the a first oxide layer in the select gate area; depositing a first in situ doped amorphous silicon layer over at least a portion of the second oxide layer, the first in situ doped amorphous silicon layer having a thickness from about 400 to about 1,000; depositing a dielectric layer over at least a portion of the first in situ doped amorphous silicon layer; depositing a second doped amorphous silicon layer over at least a portion of the dielectric layer; and forming a flash memory cell in the flash memory cell area of the substrate and a select gate transistor in the select gate area substrate, the flash memory cell comprising the second oxide layer, the first in situ doped amorphous silicon layer, the dielectric layer, and the second doped amorphous silicon layer, and the select gate transistor comprising the first oxide layer, second oxide layer, the first in situ doped amorphous silicon layer, the dielectric layer, and the second doped amorphous silicon layer.
摘要翻译： 在一个实施例中，本发明涉及一种形成NAND型快闪存储器件的方法，包括以下步骤：在衬底的至少一部分上生长第一氧化物层，所述衬底包括闪存单元区域和选择栅极 区; 去除衬底的闪存单元区域中的第一氧化物层的一部分; 在所述闪存单元区域中的所述衬底的至少一部分上以及所述选择栅极区域中的第一氧化物层的至少一部分上生长第二氧化物层; 在所述第二氧化物层的至少一部分上沉积第一原位掺杂非晶硅层，所述第一原位掺杂非晶硅层具有约400至约1,000的厚度; 在第一原位掺杂非晶硅层的至少一部分上沉积介电层; 在介电层的至少一部分上沉积第二掺杂非晶硅层; 以及在所述衬底的所述闪存单元区域中形成闪存单元，并在所述选择栅极区域衬底中形成选择栅极晶体管，所述闪存单元包括所述第二氧化物层，所述第一原位掺杂非晶硅层，所述介电层， 以及所述第二掺杂非晶硅层，以及所述选择栅极晶体管包括所述第一氧化物层，第二氧化物层，所述第一原位掺杂非晶硅层，所述介电层和所述第二掺杂非晶硅层。
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2.发明公开METHOD FOR PROVIDING A DOPANT LEVEL FOR POLYSILICON FOR FLASH MEMORY DEVICES 有权方法来实现多晶硅的一个筹资水平闪存ELEMENTS
公开(公告)号：EP1218938A1
公开(公告)日：2002-07-03
申请号：EP00948725.7
申请日：2000-07-14
IPC分类号： H01L21/8247 , H01L27/115
CPC分类号： H01L27/11521 , H01L27/11524
摘要： The present invention provides a method and a NAND-type flash memory device. The method includes forming a select gate oxide layer in a select transistor area of a substrate and a tunnel oxide layer in a memory cell area of the substrate; forming a doped amorphous silicon layer on the select gate oxide layer and the tunnel oxide layer, the doped amorphous silicon layer having a dopant level which simultaneously avoids a select transistor word line high resistance problem and a charge gain/charge loss problem; forming an insulating layer on the doped amorphous silicon layer; forming a control gate layer on the insulating layer; and etching at least the doped amorphous silicon layer, the insulating layer, and the control gate layer to form at least one memory cell stack structure and at least one select transistor stack structure. In a preferred embodiment, the polysilicon layer which forms both the floating gate of the flash memory cell and the select gate of the select transistor of the device is doped with between approximately 5 x 1018 and 8 x 1019 ions/cm3 of phosphorus. With this dopant level, the contact resistance of the select transistor's control gate is low, thus keeping the word line resistivity of the device low. Simultaneously, contamination of the tunnel oxide of the flash memory cell by the dopant is limited, allowing for the interface between the floating gate and the tunnel oxide to be smooth, which prevents charge gain/loss problems. Thus, the reliability of the device is increased.
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3.发明公开NEW METHOD OF FORMING SELECT GATE TO IMPROVE RELIABILITY AND PERFORMANCE FOR NAND TYPE FLASH MEMORY DEVICES 审中-公开新方法选通门从NAND型闪存STORE更高的可靠性和性能的生产
公开(公告)号：EP1198834A1
公开(公告)日：2002-04-24
申请号：EP00943282.4
申请日：2000-06-29
IPC分类号： H01L21/8247 , H01L27/115
CPC分类号： H01L27/11526 , H01L27/115 , H01L27/11529 , H01L27/11546
摘要： In one embodiment, the present invention relates to a method of forming a NAND type flash memory device, involving the steps of growing a first oxide layer over at least a portion of a substrate, the substrate including a core region and a periphery region, the core region including a flash memory cell area and a select gate area and the periphery region including a high voltage transistor area and low voltage transistor area; depositing a first doped amorphous silicon layer over at least a portion of the first oxide layer; depositing a dielectric layer over at least a portion of the first doped amorphous silicon layer; removing portions of the first oxide layer, the first doped amorphous silicon layer, and the dielectric layer in the select gate area of the core region and the high voltage transistor area and the low voltage transistor area the periphery region; growing a second oxide layer over at least a portion of the substrate in the select gate area of the core region and the high voltage transistor area and the low voltage transistor area the periphery region; removing portions of the second oxide layer in the select gate area of the core region and the low voltage transistor area the periphery region; growing a third oxide layer over at least a portion of the substrate in the select gate area of the core region and the low voltage transistor area of the periphery region; depositing a second doped amorphous silicon layer over at least a portion of the dielectric layer, the second oxide layer and the third oxide layer; and forming a flash memory cell in the flash memory cell area of the core region, a select gate transistor in the select gate area of the core region, a low voltage transistor in the low voltage transistor area of the periphery region, and a high voltage transistor in the high voltage transistor area of the periphery region.
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公开(公告)号：EP1145308A1
公开(公告)日：2001-10-17
申请号：EP99965057.5
申请日：1999-11-29
发明人： CAGNINA, Salvatore, F. , FANG, Hao , WANG, John, Jianshi , CHANG, Kent, Kuohua , HIGASHITANI, Masaaki
IPC分类号： H01L21/8239 , H01L21/8247
CPC分类号： H01L27/11526 , H01L27/11546
摘要： A semiconductor process for fabricating NAND type flash memory devices in a first embodiment includes step which can be performed on a production line which manufactures NOR type flash memory products. A NAND flash memory fabrication process according to a second embodiment simplifies the process and uses fewer masks, thus reducing costs and errors to produce higher yields.
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