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1.发明公开
公开(公告)号：EP1180285A1
公开(公告)日：2002-02-20
申请号：EP99967237.1
申请日：1999-12-07
IPC分类号： H04L12/44
CPC分类号： H04L49/351 , H04L49/205 , H04L49/3027 , H04L49/352 , H04L49/354 , H04L69/14
摘要： A network switch configured for switching data packets across multiple ports uses an address table to generate frame forwarding information. A decision-making engine checks the frame forwarding information to determine whether the frame is to be forwarded on a port that is part of a trunk. When the frame is to be output on a trunk port, the decision-making engine determines the port on which to transmit the frame.
摘要翻译： 配置为跨多个端口交换数据分组的网络交换机使用地址表来生成帧转发信息。 决策引擎检查帧转发信息以确定帧是否要在作为中继线一部分的端口上转发。 当帧要在中继端口上输出时，决策引擎确定要在其上发送帧的端口。
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2.发明授权APPARATUS AND METHOD FOR SHARING MEMORY USING A SINGLE RING DATA BUS CONNNECTION CONFIGURATION 有权设备和方法在配置单环数据总线连接存储器RULING
公开(公告)号：EP1266492B1
公开(公告)日：2004-09-22
申请号：EP00947599.7
申请日：2000-07-21
CPC分类号： H04L12/42
摘要： Multiple network switches are configured having memory interfaces that transfer segmented packet data to each other via a unidirectional data bus ring connecting the network switches in a single ring or "daisy chain" arrangement. The memory interfaces are also configured for transferring the segmented packet data to respective local buffer memories for temporary storage. The memory interfaces transfer the data units according to a prescribed sequence, optimizing memory bandwidth by requiring only one read and one write operation to and from the local buffer memory for each segmented packet data being received and transmitted through the switches.
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3.发明公开APPARATUS AND METHOD FOR SHARING MEMORY USING A SINGLE RING DATA BUS CONNNECTION CONFIGURATION 有权设备和方法在配置单环数据总线连接存储器RULING
公开(公告)号：EP1266492A1
公开(公告)日：2002-12-18
申请号：EP00947599.7
申请日：2000-07-21
CPC分类号： H04L12/42
摘要： Multiple network switches are configured having memory interfaces that transfer segmented packet data to each other via a unidirectional data bus ring connecting the network switches in a single ring or 'daisy chain' arrangement. The memory interfaces are also configured for transferring the segmented packet data to respective local buffer memories for temporary storage. The memory interfaces transfer the data units according to a prescribed sequence, optimizing memory bandwidth by requiring only one read and one write operation to and from the local buffer memory for each segmented packet data being received and transmitted through the switches.
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4.发明公开
公开(公告)号：EP1180284A1
公开(公告)日：2002-02-20
申请号：EP99966401.4
申请日：1999-12-17
发明人： YU, Ching , ZHUANG, Xiaohua , ERIMLI, Bahadir , CHIANG, John, M. , MERCHANT, Shashank , WILLIAMS, Robert , YANG, Edward , EGBERT, Chandan , NANDAKUMAR, Vallath , LAM, Ian , LEUNG, Eric, Tsin-Ho
IPC分类号： H04L12/44
CPC分类号： H04L49/351 , H04L49/205 , H04L49/3027 , H04L49/354
摘要： A network switch having switch ports for full-duplex communication of data packets with respective network nodes according to Ethernet (IEEE 802.3) protocol that flexibly assigns memory access slots to access an external memory according to programmable information. A scheduler within an external memory interface assigns the memory access slots to the respective network switch ports according to a programmed sequence written into an assignment table memory from an external programmable data storage device.
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