公开(公告)号：EP0223690B1

公开(公告)日：1991-01-30

申请号：EP86402466.6

申请日：1986-11-04

申请人： ALCATEL N.V.

发明人： Morton, Steven Gregory

IPC分类号： G06F15/16 ,  G06F11/20

CPC分类号： G06F15/8023 ,  G11C29/006

公开(公告)号：EP0223690A2

公开(公告)日：1987-05-27

申请号：EP86402466.6

申请日：1986-11-04

申请人： ALCATEL N.V.

发明人： Morton, Steven Gregory

IPC分类号： G06F15/16 ,  G06F11/20

CPC分类号： G06F15/8023 ,  G11C29/006

摘要： There is disclosed an array of processing elements which are arranged as a single instruction multiple data processor. Each processing cell in the array contains logic which enables the cell to determine whether or not it has been selected to perform an arithmetic or logical operation. Thus each cell in the array can obey an instruction while other cells in the array will be idle for the same instruction. The apparatus by which the processors may obey or not obey an instruction is integrated into the array of processing elements and provides stack and complement mechanisms to deal with complex sequences of tests.

摘要翻译： 公开了一组处理元件，其被配置为单个指令多数据处理器。 阵列中的每个处理单元包含使单元能够确定是否被选择执行算术或逻辑运算的逻辑。 因此，阵列中的每个单元都可以遵循指令，而阵列中的其他单元将为相同的指令空闲。 处理器可以服从或不服从指令的装置被集成到处理元件阵列中，并提供堆栈和补码机制来处理复杂的测试序列。

公开(公告)号：EP0121763A2

公开(公告)日：1984-10-17

申请号：EP84102380.7

申请日：1984-03-06

申请人： ALCATEL N.V.

发明人： Morton, Steven Gregory ,  Cotton, John Michael

IPC分类号： G06F15/16

CPC分类号： G06F15/8023 ,  G06F15/8038

摘要： An associative array processor is described wherein an array (ARRAY) of associative processing cells is configured according to a format defined by configuration bits which perform functions previously performed by external masks.
The array of associative processing cells is intervened by five paths, the minimum number of interconnections between adjacent horizontal cells.
A transversal horizontal multiplexer is described which allows an arbitrary number of these devices to be connected to series. Each of these transversal horizontal multiplexers forms a part of a processing cell and allows a variety of communications between adjacent processing cells.

摘要翻译： 描述了一种关联阵列处理器，其中根据由执行先前由外部掩码执行的功能的配置位定义的格式来配置关联处理单元的阵列（ARRAY）。 关联处理单元的阵列被五个路径介入，相邻水平单元之间的最小互连数。 描述了横向水平多路复用器，其允许任意数量的这些装置串联连接。 这些横向水平多路复用器中的每一个形成处理单元的一部分并且允许相邻处理单元之间的各种通信。

公开(公告)号：EP0121763B1

公开(公告)日：1990-08-22

申请号：EP84102380.7

申请日：1984-03-06

申请人： ALCATEL N.V.

发明人： Morton, Steven Gregory ,  Cotton, John Michael

IPC分类号： G06F15/16

CPC分类号： G06F15/8023 ,  G06F15/8038

公开(公告)号：EP0121763A3

公开(公告)日：1988-01-27

申请号：EP84102380

申请日：1984-03-06

申请人： ALCATEL N.V.

发明人： Morton, Steven Gregory ,  Cotton, John Michael

IPC分类号： G06F15/06

CPC分类号： G06F15/8023 ,  G06F15/8038

摘要： An associative array processor is described wherein an array (ARRAY) of associative processing cells is configured according to a format defined by configuration bits which perform functions previously performed by external masks. The array of associative processing cells is intervened by five paths, the minimum number of interconnections between adjacent horizontal cells. A transversal horizontal multiplexer is described which allows an arbitrary number of these devices to be connected to series. Each of these transversal horizontal multiplexers forms a part of a processing cell and allows a variety of communications between adjacent processing cells.