利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

5 条记录 (耗时 0.009 秒)

    Multiplier/adder circuit
    3.
    发明公开
    Multiplier/adder circuit 失效
    Multiplikations-添置-Schaltung。

    公开(公告)号：EP0095216A2

    公开(公告)日：1983-11-30

    申请号：EP83200725.6

    申请日：1983-05-25

    申请人： AMERICAN MICROSYSTEMS, INCORPORATED

    发明人： Amir, Gideon ,  Gregorian, Roubik

    IPC分类号： H03H21/00 ,  G10L3/00

    CPC分类号： H03H21/0007 ,  G06J1/00 ,  G10L19/16 ,  H03H19/004

    摘要： This invention provides a uniquely designed switched capacitor multiplier/adder (129) which also functions as a digital-to-analog converter in a single subcircuit. The multiplier/adder, in a single operation, multiplies an analog voltage by a binary coefficient, and sums this product with a second analog voltage. The use of this unique subcircuit significantly reduces the space requirements for the construction of, for example, a speech synthesis circuit utilizing linear predictive coding over prior art circuits. This size reduction in turn significantly reduces the manufacturing costs for this circuit over prior art circuits, and additionally allows the option of including on the speech synthesis chip a memory for the storage of binary representations of to-be-synthesized speech patterns.
    In one embodiment of this invention, a novel structure and method are provided which minimize error components in the synthesized speech signal due to voltage errors inherent in the use of analog sample and hold circuits which are used to store the forward and backward prediction errors utilized in the linear predictive coding technique.

    摘要翻译： 本发明提供了一种独特设计的开关电容器乘法器/加法器（129），其也在单个子电路中用作数模转换器。 乘法器/加法器在单个操作中，将模拟电压乘以二进制系数，并将该乘积与第二模拟电压相加。 使用这种独特的分支电路显着地减少了构建例如利用现有技术电路的线性预测编码的语音合成电路的空间要求。 这种尺寸减小又显着地降低了该电路相对于现有技术电路的制造成本，并且还允许在语音合成芯片上包括用于存储待合成语音模式的二进制表示的存储器的选项。 ...在本发明的一个实施例中，提供了一种新颖的结构和方法，其使合成语音信号中的误差分量最小化，这是由于使用模拟采样和保持电路固有的电压误差，其用于存储前向和 在线性预测编码技术中使用的后向预测误差。

    Gain stage with operational amplifier and switched capacitor resistor equivalent circuit
    4.
    发明公开
    Gain stage with operational amplifier and switched capacitor resistor equivalent circuit 失效
    用运算放大器和具有可切换电容器的等效电阻电路放大器级。

    公开(公告)号：EP0060026A1

    公开(公告)日：1982-09-15

    申请号：EP82300616.8

    申请日：1982-02-08

    申请人： AMERICAN MICROSYSTEMS, INCORPORATED

    发明人： Amir, Gideon ,  Haque, Yusuf ,  Gregorian, Roubik

    IPC分类号： H03F1/30

    CPC分类号： H03F1/303

    摘要： An operational amplifier gain stage incorporating switched capacitor resistor equivalent circuits uses a delayed clock reference signal (φ D , φ D ) to eliminate the effects of spurious error voltages (E s ) generated when utilizing metal oxide silicon field effect transistors as switches (12, 15, 21, 23, 25). The single remaining MOSFET switch (21) which will contribute a spurious voltage component to the output of the operational amplifier gain stage is designed in such a manner as to minimize the spurious voltage generated during operation of the MOSFET switch. A single dummy switch (31) is utilized to further minimise the spurious voltage generated by this single MOSFET switch.

    Multiplier/adder circuit
    5.
    发明公开
    Multiplier/adder circuit 失效
    多路复用器/ ADDER电路

    公开(公告)号：EP0095216A3

    公开(公告)日：1985-10-30

    申请号：EP83200725

    申请日：1983-05-25

    申请人： AMERICAN MICROSYSTEMS, INCORPORATED

    发明人： Amir, Gideon ,  Gregorian, Roubik

    IPC分类号： H03H21/00 ,  G10L01/08

    CPC分类号： H03H21/0007 ,  G06J1/00 ,  G10L19/16 ,  H03H19/004

    摘要： This invention provides a uniquely designed switched capacitor multiplier/adder (129) which also functions as a digital-to-analog converter in a single subcircuit. The multiplier/adder, in a single operation, multiplies an analog voltage by a binary coefficient, and sums this product with a second analog voltage. The use of this unique subcircuit significantly reduces the space requirements for the construction of, for example, a speech synthesis circuit utilizing linear predictive coding over prior art circuits. This size reduction in turn significantly reduces the manufacturing costs for this circuit over prior art circuits, and additionally allows the option of including on the speech synthesis chip a memory for the storage of binary representations of to-be-synthesized speech patterns. In one embodiment of this invention, a novel structure and method are provided which minimize error components in the synthesized speech signal due to voltage errors inherent in the use of analog sample and hold circuits which are used to store the forward and backward prediction errors utilized in the linear predictive coding technique.