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1.发明公开
公开(公告)号：EP0295896A2
公开(公告)日：1988-12-21
申请号：EP88305472.8
申请日：1988-06-15
CPC分类号： H04B3/58 , H02J13/0034 , H04B3/542 , H04B2203/5416 , H04B2203/5425 , H04B2203/5483 , H04B2203/5491 , H04B2203/5495 , Y02E60/7892 , Y04S40/146
摘要： An apparatus for controlling the output of a switching amplifier (38) includes a signal dividing circuit (14) which generates a delayed replica (S1) of the carrier signal and a doubled signal (S2) having twice the carrier frequency. The doubled signal is effective for establishing a second time delayed signal relative to the first time delayed signal (S1A). The first and second time delayed signals are logically operated on so that a three state output representing the carrier signal is attained. A summing amplifier (26) utilizes the two time delayed signals to generate this three state output whereby if the two time delayed signals are out-of-phase, a zero voltage is connected to the drive portion (40, 42) of the switching amplifier thereby limiting the output of the switching amplifier.
摘要翻译： 用于控制开关放大器（38）的输出的装置包括产生载波信号的延迟复制（S1）的信号分割电路（14）和具有两倍载波频率的双倍信号（S2）。 双倍信号对于建立相对于第一时间延迟信号（S1A）的第二时间延迟信号是有效的。 逻辑上操作第一和第二时间延迟信号，从而获得表示载波信号的三态输出。 一个加法放大器（26）利用两个时间延迟的信号产生这个三态输出，由此如果两个时间延迟的信号是异相的，零电压被连接到开关放大器的驱动部分（40,42） 从而限制开关放大器的输出。
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公开(公告)号：EP0153165A2
公开(公告)日：1985-08-28
申请号：EP85301012.2
申请日：1985-02-15
CPC分类号： H04B3/542 , H04B2203/5466 , H04B2203/5483 , H04B2203/5491 , H04B2203/5495
摘要： A time diversity carrier signal sampler utilizes a shift register [Figs. 6, 7 (70); Fig 8 (170)] in conjunction with a timer (190) and a plurality of phase samples [Fig. 7 (61, 62, 63); Fig. 8 (196, 197, 198)]. The instantaneous logic level of each phase is measured on a time diversity basis in orderto avoid the disadvantageous affects of noise pulses [Fig. 5 (54, 55)] which can occur coincidently on all three phases. The resulting carrier signal data is then provided [Fig. 8 (199)] to a microprocessor [Fig. 7 (80); Fig. 8 [(180)] for subsequent analysis and phase characteristic determinations. By judiciously selecting the sample and clock frquencies of the shift register, the sampling frequency for each phase and the time between sampling each of the phases can be preselected.
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公开(公告)号：EP0153165B1
公开(公告)日：1990-12-12
申请号：EP85301012.2
申请日：1985-02-15
CPC分类号： H04B3/542 , H04B2203/5466 , H04B2203/5483 , H04B2203/5491 , H04B2203/5495
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公开(公告)号：EP0295896A3
公开(公告)日：1990-10-17
申请号：EP88305472.8
申请日：1988-06-15
CPC分类号： H04B3/58 , H02J13/0034 , H04B3/542 , H04B2203/5416 , H04B2203/5425 , H04B2203/5483 , H04B2203/5491 , H04B2203/5495 , Y02E60/7892 , Y04S40/146
摘要： An apparatus for controlling the output of a switching amplifier (38) includes a signal dividing circuit (14) which generates a delayed replica (S1) of the carrier signal and a doubled signal (S2) having twice the carrier frequency. The doubled signal is effective for establishing a second time delayed signal relative to the first time delayed signal (S1A). The first and second time delayed signals are logically operated on so that a three state output representing the carrier signal is attained. A summing amplifier (26) utilizes the two time delayed signals to generate this three state output whereby if the two time delayed signals are out-of-phase, a zero voltage is connected to the drive portion (40, 42) of the switching amplifier thereby limiting the output of the switching amplifier.
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