公开(公告)号：EP2138931A1

公开(公告)日：2009-12-30

申请号：EP09012998.2

申请日：2004-03-22

申请人： ATMEL CORPORATION

发明人： Dupaquis, Vincent ,  Paris, Laurent

IPC分类号： G06F7/72 ,  G06F7/52

CPC分类号： G06F7/5318 ,  G06F7/724

摘要： An integrated circuit parallel multiplication circuit delivers both natural multiplication products and polynomial products with coefficients over GF(2). The parallel multiplier hardware architecture ( Fig. 3 ) arranges the addition of partial products (Pi, j) so that it begins in a first group of adder stages (23) that perform additions without receiving any carry terms as inputs, and so that addition of the carry terms (e k+1 ) is deferred until a second group of adder stages (29) is arranged to follow the first group. This intentional arrangement of the adders into two separate groups allows both the polynomial product (d k ) to be extracted from the results (s k ) of the first group of additions, and the natural product (c k ) to be extracted from the results of the second group of additions.

摘要翻译： 集成电路并行乘法电路提供GF（2）上的系数的自然乘积和多项式乘积。 并行乘法器硬件体系结构（图3）排列了部分乘积（Pi，j）的加法，使得它开始于第一组加法器级（23），它们在不接收任何进位项作为输入的情况下执行加法， 的进位项（e k + 1）被推迟直到第二组加法器级（29）被布置成跟随第一组。 将加法器有意排列成两个单独的组允许从第一组添加的结果（sk）中提取多项式乘积（dk），并且从第二组的结果中提取天然产物（ck） 一组添加。