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公开(公告)号：EP4418053A1
公开(公告)日：2024-08-21
申请号：EP23163316.5
申请日：2023-03-21
IPC分类号： G04F10/00
CPC分类号： G04F10/005
摘要： An apparatus for clockless and direct conversion of a time interval to a digital word comprises: a control module (CM), two comparators (KR, KS), two current sources (IR, IS), two buses (R, S), two counter capacitors Cn-r, a set of n-r capacitors (Cn-r-1, ..., C0) with a binary capacitance ratio, two counter switches (Sn-r) and n-r switches of a set (Sn-r-1, ..., S0). The control module (CM) is equipped with an r-bit counter (Ct), whose outputs are connected directly to outputs of r most significant bits (bn-1, ..., br) of the n-bit output digital word (B).
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公开(公告)号：EP4418054A1
公开(公告)日：2024-08-21
申请号：EP23163317.3
申请日：2023-03-21
IPC分类号： G04F10/00
CPC分类号： G04F10/005
摘要： A method for clockless and direct conversion of a time interval to a digital word is characterized in that the converted time interval (T) is mapped in the form of a difference between a reference time period (RT) and a signal time period (ST), a sum of lengths of which is approximately proportional to the length of the converted time interval (T). The reference time period (RT) is first measured roughly using linear method, and next precisely by method of weight compensation.
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公开(公告)号：EP4261623A1
公开(公告)日：2023-10-18
申请号：EP22213666.5
申请日：2022-12-15
摘要： A method for recognizing an order of signals by means of a main MUTEX circuit is characterized in that metastability of the main MUTEX circuit (MM x ) is detected and is signaled by means of an additional MUTEX circuit (MA x ). If metastability of the main MUTEX circuit (MM x ) is detected, default values are assigned to an appropriate bit group of an output digital word (B) by means of an output module (OM).
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公开(公告)号：EP4261622A1
公开(公告)日：2023-10-18
申请号：EP22213665.7
申请日：2022-12-15
IPC分类号： G04F10/00
摘要： A system for recognizing an order of signals comprise a main MUTEX circuit (MM x ), a first delay circuit (T M1x ), a second delay circuit (T M1x ) and a path configuration circuit (E x ). The system is characterized in that inputs of the main MUTEX circuit (MM x ) are connected to inputs of a first gate (B1), whose output is connected to an additional delay circuit (T Dx ), and its output is connected to a reset input (R) of an additional MUTEX circuit (MA x ). Outputs of the main MUTEX circuit (MM x ) are connected to inputs of a second gate (B2), whose output is connected to a set input (S) of the additional MUTEX circuit (MA x ). A second output (Q2) of the additional MUTEX circuit (MA x ) is connected to a priority input (Prt x ) of an output module (OM).
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