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公开(公告)号:EP3257045A1
公开(公告)日:2017-12-20
申请号:EP15882269.2
申请日:2015-12-17
申请人: Apple Inc.
CPC分类号: G10L15/28 , G10L15/08 , G10L15/22 , G10L2015/088 , G10L2015/223
摘要: In an embodiment, a system on a chip (SOC) may include one or more central processing units (CPUs), a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples and match those audio samples against a predetermined pattern. The circuit may operate according to a first clock during the time that the rest of the SOC is powered down. In response to detecting the predetermined pattern in the samples, the circuit may cause the memory controller and processors to power up. During the power up process, a second clock having one or more better characteristics than the first clock may become available. The circuit may switch to the second clock while preserving the samples, or losing at most one sample, or no more than a threshold number of samples.
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