公开(公告)号：EP4411552A1

公开(公告)日：2024-08-07

申请号：EP24154336.2

申请日：2024-01-29

申请人： Avago Technologies International Sales Pte. Limited

发明人： Mitra, Bhaswar ,  Birman, Mark

IPC分类号： G06F12/14

CPC分类号： G06F12/1408 ,  G06F2212/105220130101

摘要： A system including memory, a lookup circuit and an address circuit. The memory can store a plurality of tables. Each table can have a plurality of entries and each entry can have an entry index. The lookup circuit can be coupled with the memory. The lookup circuit can provide the plurality of entry indexes of the plurality of tables to the address circuit. The address circuit can include a first circuit, a second circuit, and third circuit. The first circuit can include a plurality of entry scramblers. The second circuit can include a plurality of translators, and the third circuit can include a plurality of row scramblers.