公开(公告)号：EP3627711A1

公开(公告)日：2020-03-25

申请号：EP19196966.6

申请日：2019-09-12

申请人： Avago Technologies International Sales Pte. Limited

发明人： Tu, Chungming ,  Souvignier, Thomas V. ,  Darabiha, Ahmad

IPC分类号： H03M13/15 ,  H03M13/27 ,  H03M13/00

摘要： An interleaved encoder includes a number of encoders consisting of L parallel encoders, and a first switch circuit to sequentially couple an input node to an input port of one of the encoders. The input node receives a group of K*L symbols. Each symbol of the group of K*L symbols is received in synch with a respective clock pulse of a group of K*L clock pulses. The first switch circuit is synched with clock pulses of the group of K*L clock pulses, and sequentially couples the input node to an input port of a subsequent one of the encoders in response to each clock pulse of the group of K*L clock pulses.