DISPLAY SUBSTRATE AND DISPLAY APPARATUS
    1.
    发明公开

    公开(公告)号:EP4421791A1

    公开(公告)日:2024-08-28

    申请号:EP22947218.8

    申请日:2022-06-21

    IPC分类号: G09G3/3208 G09G3/3225

    CPC分类号: G09G3/3225 G09G3/3208

    摘要: A display substrate and a display apparatus. The display substrate comprises: a base and a circuit structure layer arranged thereon. The circuit structure layer comprises pixel circuits (P), a scan driving circuit, a control driving circuit and a buffer driving circuit. Each pixel circuit (P) comprises: a node reset transistor (T1), a write-in transistor (T4), a reset signal line (RL), a scan signal line (GL) and a control signal line (SL), the reset signal line (RL) being connected to a control electrode of the node reset transistor (T1), and the scan signal line (GL) being connected to a control electrode of the write-in transistor (T4). The reset signal lines (RL1-RLK) of the pixel circuits (P) in first to Kth rows are electrically connected to the buffer driving circuit, and the reset signal lines (RLK+1-RLN) of the pixel circuits (P) in (K+1)th to Nth rows are electrically connected to the scan driving circuit or the control driving circuit, K allowing, of a pixel circuit (P), a difference between the start time of an active level of a signal on the scan signal line (GL) or on the control signal line (SL) and the end time of an active level of a signal on the reset signal line (RL) to be greater than or equal to a threshold time.

    DISPLAY SUBSTRATE AND DISPLAY APPARATUS
    2.
    发明公开

    公开(公告)号:EP4415022A1

    公开(公告)日:2024-08-14

    申请号:EP22939257.6

    申请日:2022-04-29

    IPC分类号: H01L

    摘要: A display substrate and a display apparatus. The display substrate comprises a display area and a non-display area, and the non-display area comprises a rounded corner area. The display substrate comprises a circuit structure layer, and the circuit structure layer comprises a pixel circuit and a control driving circuit. The circuit structure layer further comprises: a plurality of reset output wires and a plurality of reset patch wires located in the non-display area and disposed on the side of the control driving circuit adjacent to the display area. The reset output wires and the reset patch wires are arranged in different layers, and an extension direction of the reset output wires intersects with an extension direction of the reset patch wires; the reset patch wires are connected to the pixel circuit; and the orthographic projection of the at least one reset patch wire located in the rounded corner area on the substrate partially overlaps with the orthographic projection of the plurality of reset output wires on the substrate.