摘要:
A digital audio signal which is subject to sample-to-sample jitter is synchronised with local reference pulses (READ) by the use of a read-write buffer memory (12). Timing pulses at a terminal (80) are associated with the input samples. The input samples are applied through a one-sample latch store (36) to the main memory (12), and the timing pulses are applied by switches (66,68) either directly or after a short delay by a delay element (38) to the write control input of the main memory (12). A phase comparator (24) detects sample-by-sample when the write pulses are near to the read pulses and causes the switches (66,68) to change state in response thereto, and they retain their changed state until a danger of potential read-write contention is again detected when they revert to their original state.
摘要:
A biphase-mark coded digital audio signal comprising short and long pulses (IEC 958) is decoded despite substantial variation of sample rate but without a separate synchronisation or timing signal and without a phase locked loop. The pulse lengths are measured (14) and then compared (22,20) with two thresholds. One (22) is a variable threshold derived by generator (26) as 1.5 times the average length of the short pulses, this average being stored in register (28). This will normally be adequate to discriminate the short and long pulses. The second comparison (20) is with a fixed value which is lower than 1.5 times the pulse length at the highest input frequency. When the comparators disagree irreconcilably in their determination, the resultant of the second comparison is used instead of the first. This allows the system to respond quickly to start-up or sudden change in input data rate.
摘要:
A digital audio signal which is subject to sample-to-sample jitter is synchronised with local reference pulses (READ) by the use of a read-write buffer memory (12). Timing pulses at a terminal (80) are associated with the input samples. The input samples are applied through a one-sample latch store (36) to the main memory (12), and the timing pulses are applied by switches (66,68) either directly or after a short delay by a delay element (38) to the write control input of the main memory (12). A phase comparator (24) detects sample-by-sample when the write pulses are near to the read pulses and causes the switches (66,68) to change state in response thereto, and they retain their changed state until a danger of potential read-write contention is again detected when they revert to their original state.
摘要:
A biphase-mark coded digital audio signal comprising short and long pulses (IEC 958) is decoded despite substantial variation of sample rate but without a separate synchronisation or timing signal and without a phase locked loop. The pulse lengths are measured (14) and then compared (22,20) with two thresholds. One (22) is a variable threshold derived by generator (26) as 1.5 times the average length of the short pulses, this average being stored in register (28). This will normally be adequate to discriminate the short and long pulses. The second comparison (20) is with a fixed value which is lower than 1.5 times the pulse length at the highest input frequency. When the comparators disagree irreconcilably in their determination, the resultant of the second comparison is used instead of the first. This allows the system to respond quickly to start-up or sudden change in input data rate.