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    MPEG error concealment
    2.
    发明公开
    MPEG error concealment 审中-公开
    FehlerverschleierungfürMPEG

    公开(公告)号：EP1335604A2

    公开(公告)日：2003-08-13

    申请号：EP03001894.9

    申请日：2003-01-29

    申请人： Broadcom Corporation

    发明人： Demas, Jason ,  Bhatia, Sandeep ,  Chen, Sherman Xuemin ,  Reddy, Srinivasa Mogathala Prabhakara ,  Humlani, Girish Raghunath ,  Kellerman, Marcus ,  Valmiki, Ramanujan ,  Pai, Lakshmikanth ,  Chandraiah, Pramod ,  Sivagururaman, Mahadevan ,  Grover, Glen A.

    IPC分类号： H04N7/24

    CPC分类号： H04N19/895 ,  H04N19/65 ,  H04N19/89 ,  H04N21/23608 ,  H04N21/4147 ,  H04N21/4325 ,  H04N21/4344 ,  H04N21/440245 ,  H04N21/442

    摘要： Error concealment for motion picture expert group (MPEG) decoding with personal video recording functionality. Error concealment of MPEG data is performed within various components within playback, recording, reading and writing data systems. This error concealment is operable within existing systems whose components may not be capable of accommodating errors within MPEG data. Whereas prior art systems typically cannot deal with any corruption without either losing the data or suffering some operational failure, this approach is able to conceal these errors and to continue decoding and presentation of the MPEG data. In certain embodiments, this involves maximizing the available data that contain no errors to conceal those portions of the data that do include errors. This approach is operable to accommodate various layers while performing error concealment, including the MPEG transport stream layer, the video layer, and the audio layer.

    摘要翻译： 用于具有个人视频录制功能的电影专家组（MPEG）解码的错误隐藏。 MPEG数据的错误隐藏在播放，记录，读取和写入数据系统内的各种组件内执行。 该错误隐藏在现有系统中可操作，其组件可能无法适应MPEG数据中的错误。 而现有技术系统通常不能处理任何损坏而不丢失数据或遭受一些操作故障，这种方法能够隐藏这些错误并继续解码和呈现MPEG数据。 在某些实施例中，这涉及最大化包含没有错误的可用数据以隐藏包括错误的数据的那些部分。 该方法可操作以适应各种层，同时执行错误隐藏，包括MPEG传输流层，视频层和音频层。

    A method and apparatus for implementing reduced memory mode for high-definition television
    4.
    发明公开
    A method and apparatus for implementing reduced memory mode for high-definition television 有权
    在用于高清晰度电视减小的模式存储的方法和装置

    公开(公告)号：EP1292154A2

    公开(公告)日：2003-03-12

    申请号：EP02090296.1

    申请日：2002-08-20

    申请人： Broadcom Corporation

    发明人： Chen, sherman (Xuemin) ,  Demas, Jason ,  Bhatia, Sandeep

    IPC分类号： H04N7/50

    CPC分类号： H04N19/90 ,  H04N19/126 ,  H04N19/159 ,  H04N19/162 ,  H04N19/172 ,  H04N19/174 ,  H04N19/428 ,  H04N19/61

    摘要： A method and apparatus are provided for implementing an enhanced reduced memory mode (RMM) of decoding HDTV MPEG-2 video stream. In one instance, the RMM mode is adaptively enabled with up/down conversion by using the picture-type information. In another instance, the RMM mode is provided by performing anchor-frame compression/decompression by using adaptive DPCM technique with picture-type information. The quantization (PCM) tables are generated using the Lloyd algorithm. Further, the predictor for each pixel is determined by a use of the Graham rule.

    摘要翻译： 提供了用于实现解码HDTV MPEG-2视频流的增强减小memorymode（RMM）的方法和装置。 在一个实例中，RMM模式自适应地向上/向下转换通过使用画面类型信息启用。 在另一实例中，RMM模式是通过使用自适应DPCM技术与画面类型信息执行锚帧压缩/解压缩提供的。 该算法量化（PCM）表可以使用劳埃德生成。 此外，每个像素的预测值确定的通过使用格雷厄姆规则的开采。

    Multistandard video decoder
    6.
    发明公开
    Multistandard video decoder 审中-公开
    Multistandardvideodekodierer

    公开(公告)号：EP1562383A3

    公开(公告)日：2005-08-17

    申请号：EP05002311.8

    申请日：2005-02-03

    申请人： Broadcom Corporation

    发明人： Bidnur, Ravindra ,  Pai, Lakshmikanth Ramadas ,  Sherigar, Bhaskar ,  Sane, Anirudda ,  Bhatia, Sandeep ,  Agarwal, Gaurav

    IPC分类号： H04N7/26 ,  H04N7/50 ,  G06F9/38

    CPC分类号： H04N19/44 ,  H04N19/61 ,  H04N19/70

    摘要： Presented herein is a unified decoder architecture. A system comprises a video decoder, instruction memory, and a host processor. The video decoder decodes the video data encoded with the particular standard. The instruction memory stores a first set of instructions and a second set of instructions. The first set of instructions are for decoding encoded video data according to a first encoding standard. The second set of instruction are for decoding encoded video data according to a second encoding standard. The host processor provides an indication to the video decoder indicating the particular encoding standard. The video decoder executes the first set of instructions if the indication indicates that the particular encoding standard is the first encoding standard and executes the second set of instructions if the indication indicates that the particular encoding standard is the second encoding standard. The encoding standards can be MPEG-2, MPEG-4, DV-25.

    Multistandard video decoder
    7.
    发明公开
    Multistandard video decoder 审中-公开
    多标准视频解码器

    公开(公告)号：EP1562383A2

    公开(公告)日：2005-08-10

    申请号：EP05002311.8

    申请日：2005-02-03

    申请人： Broadcom Corporation

    发明人： Bidnur, Ravindra ,  Pai, Lakshmikanth Ramadas ,  Sherigar, Bhaskar ,  Sane, Anirudda ,  Bhatia, Sandeep ,  Agarwal, Gaurav

    IPC分类号： H04N7/26 ,  H04N7/50 ,  G06F9/38

    CPC分类号： H04N19/44 ,  H04N19/61 ,  H04N19/70

    摘要： Presented herein is a unified decoder architecture. A system comprises a video decoder, instruction memory, and a host processor. The video decoder decodes the video data encoded with the particular standard. The instruction memory stores a first set of instructions and a second set of instructions. The first set of instructions are for decoding encoded video data according to a first encoding standard. The second set of instruction are for decoding encoded video data according to a second encoding standard. The host processor provides an indication to the video decoder indicating the particular encoding standard. The video decoder executes the first set of instructions if the indication indicates that the particular encoding standard is the first encoding standard and executes the second set of instructions if the indication indicates that the particular encoding standard is the second encoding standard. The encoding standards can be MPEG-2, MPEG-4, DV-25.

    摘要翻译： 这里呈现的是统一的解码器架构。 一个系统包括视频解码器，指令存储器和主处理器。 视频解码器解码用特定标准编码的视频数据。 指令存储器存储第一组指令和第二组指令。 第一组指令用于根据第一编码标准对经编码的视频数据进行解码。 第二组指令用于根据第二编码标准对经编码的视频数据进行解码。 主处理器向视频解码器提供指示特定编码标准的指示。 如果指示指示特定编码标准是第一编码标准，则视频解码器执行第一指令集，并且如果指示指示特定编码标准是第二编码标准，则执行第二指令集。 编码标准可以是MPEG-2，MPEG-4，DV-25。