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1.发明公开Apparatus and method for address translation of non-aligned double word virtual addresses 失效用于寻址非对齐双字虚拟地址的装置和方法
公开(公告)号：EP0377431A3
公开(公告)日：1992-01-22
申请号：EP90100011.7
申请日：1990-01-02
CPC分类号： G06F12/0886 , G06F12/10 , G06F12/1491 , G06F2212/655
摘要： In a data processing system in which the execution unit is implemented to process aligned double word operands, apparatus and an associated method provide for the alignment of a double word operand that is stored across a double word boundary. The two double words each storing a word of the unaligned double word operand are identified and the attributes are compared with the ring number of the associated program. When the comparisons indicate that the two words of the non-aligned double word operand are available to the program, the two double word operands containing non-aligned words of the double word operand, and the two non-aligned words are stored in a register in an aligned orientation for processing by the execution unit.
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公开(公告)号：EP0389886A3
公开(公告)日：1991-12-11
申请号：EP90104975.9
申请日：1990-03-16
IPC分类号： G06F12/14
CPC分类号： G06F12/1491
摘要： During the execution of an instruction by an execution unit, the instruction is stored in an instruction register, the operand including its ring number is stored in a data register and the ring number developed by the Virtual Memory Management Unit is stored in a ring effective register. The instruction addresses a control store which stores a firmware word in a control store register. A firmware field is decoded to generate a plurality of ring control signals. The ring numbers from the data and ring effective registers are compared and an effective ring number is generated. Depending on the states of the secure process signal, the ring control signals and the relative value of the ring numbers, the effective ring number is binary 00 or the larger ring number.
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3.发明公开Apparatus and method for address translation of non-aligned double word virtual addresses 失效装置和方法用于转换的虚拟地址的非对准双字。
公开(公告)号：EP0377431A2
公开(公告)日：1990-07-11
申请号：EP90100011.7
申请日：1990-01-02
CPC分类号： G06F12/0886 , G06F12/10 , G06F12/1491 , G06F2212/655
摘要： In a data processing system in which the execution unit is implemented to process aligned double word operands, apparatus and an associated method provide for the alignment of a double word operand that is stored across a double word boundary. The two double words each storing a word of the unaligned double word operand are identified and the attributes are compared with the ring number of the associated program. When the comparisons indicate that the two words of the non-aligned double word operand are available to the program, the two double word operands containing non-aligned words of the double word operand, and the two non-aligned words are stored in a register in an aligned orientation for processing by the execution unit.
摘要翻译： 在其中执行单元实现为处理对准双字操作数，装置和相关方法，以提供一个双字操作数的对准的数据处理系统也被存储跨越双字边界。 存放未对齐双字操作数的一个字中的两个双字的每个被识别和属性与相关联的程序的环号相比。 当比较指示DASS死非对准双字操作数的两个词对程序可用，两个双字操作数包含双字操作数的非对齐的字，和两个非对齐的字被存储在一寄存器 在由所述执行单元用于处理对准取向。
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公开(公告)号：EP0389886A2
公开(公告)日：1990-10-03
申请号：EP90104975.9
申请日：1990-03-16
IPC分类号： G06F12/14
CPC分类号： G06F12/1491
摘要： During the execution of an instruction by an execution unit, the instruction is stored in an instruction register, the operand including its ring number is stored in a data register and the ring number developed by the Virtual Memory Management Unit is stored in a ring effective register. The instruction addresses a control store which stores a firmware word in a control store register. A firmware field is decoded to generate a plurality of ring control signals. The ring numbers from the data and ring effective registers are compared and an effective ring number is generated. Depending on the states of the secure process signal, the ring control signals and the relative value of the ring numbers, the effective ring number is binary 00 or the larger ring number.
摘要翻译： 在由执行单元执行指令期间，该指令被存储在指令寄存器中，包括其环号的操作数存储在数据寄存器中，由虚拟存储器管理单元开发的环编号存储在环形有效寄存器 。 该指令寻址一个控制存储器，其将固件字存储在控制存储寄存器中。 固件字段被解码以产生多个环控制信号。 比较来自数据和环形有效寄存器的振铃数，并产生有效振铃号。 根据安全过程信号的状态，环控制信号和环号的相对值，有效环数为二进制00或较大的环号。
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5.发明授权Apparatus and method for address translation of non-aligned double word virtual addresses 失效装置和方法用于平移的非对准双字虚拟地址
公开(公告)号：EP0377431B1
公开(公告)日：1999-05-26
申请号：EP90100011.7
申请日：1990-01-02
CPC分类号： G06F12/0886 , G06F12/10 , G06F12/1491 , G06F2212/655
摘要： In a data processing system in which the execution unit is implemented to process aligned double word operands, apparatus and an associated method provide for the alignment of a double word operand that is stored across a double word boundary. The two double words each storing a word of the unaligned double word operand are identified and the attributes are compared with the ring number of the associated program. When the comparisons indicate that the two words of the non-aligned double word operand are available to the program, the two double word operands containing non-aligned words of the double word operand, and the two non-aligned words are stored in a register in an aligned orientation for processing by the execution unit.
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公开(公告)号：EP0389886B1
公开(公告)日：1999-05-12
申请号：EP90104975.9
申请日：1990-03-16
IPC分类号： G06F12/14
CPC分类号： G06F12/1491
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公开(公告)号：EP0232526B1
公开(公告)日：1993-03-31
申请号：EP86117604.8
申请日：1986-12-17
CPC分类号： G06F12/0882 , G06F12/0831 , G06F12/1063
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公开(公告)号：EP0232526A3
公开(公告)日：1989-08-30
申请号：EP86117604.8
申请日：1986-12-17
CPC分类号： G06F12/0882 , G06F12/0831 , G06F12/1063
摘要： A multiprocessor computer system includes a main memory and a plurality of central processing units (CPU's) which are connected to share main memory via a common bus network. Each CPU has instruction and data cache units, each organized on a page basis for complete operating compatibility with user processes. Each cache unit includes a number of content addressable memories (CAM's) and directly addressable memories (RAM's) organized to combine associative and direct mapping of data or instructions on a page basis. An input CAM in response to a CPU address provides a cache address which includes a page level number for identifying where all of the required information resides in the other memories for processing requests relating to the page. This organization permits the processing of either virtual or physical addresses with improved speed and reduced complexity and the ability to detect and eliminate both consistency and synonym problems.
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公开(公告)号：EP0232526A2
公开(公告)日：1987-08-19
申请号：EP86117604.8
申请日：1986-12-17
CPC分类号： G06F12/0882 , G06F12/0831 , G06F12/1063
摘要： A multiprocessor computer system includes a main memory and a plurality of central processing units (CPU's) which are connected to share main memory via a common bus network. Each CPU has instruction and data cache units, each organized on a page basis for complete operating compatibility with user processes. Each cache unit includes a number of content addressable memories (CAM's) and directly addressable memories (RAM's) organized to combine associative and direct mapping of data or instructions on a page basis. An input CAM in response to a CPU address provides a cache address which includes a page level number for identifying where all of the required information resides in the other memories for processing requests relating to the page. This organization permits the processing of either virtual or physical addresses with improved speed and reduced complexity and the ability to detect and eliminate both consistency and synonym problems.
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