公开(公告)号：EP0792486A1

公开(公告)日：1997-09-03

申请号：EP95923926.0

申请日：1995-06-16

申请人： CRAY RESEARCH, INC.

发明人： WEST, Jeffrey, D.

IPC分类号： G01R31

CPC分类号： G01R31/318552

摘要： A test access port controller for use in a level sensitive scan design having test design logic including at least one serial scan test path. The test access port controller includes test access port controller logic operable in a system test mode for controlling the serial shifting of input test data into the at least one serial scan test path and for controlling serial shifting of resulting output test data out of the at least one serial scan test path after performance of system mode test under control of a test clock. The test access port controller further includes clock logic for providing the test clock to the test access port controller logic and the test design logic in system test mode. The clock logic further provides a system clock to the test access port controller logic and test design logic in a fabrication test mode to serially shift input test data into the test access port controller logic and test design logic and to serially shift resulting output data out of the test access port controller logic and test design logic after operation of the test access port controller logic and test design logic under one cycle of test clock. A test method for such level sensitive scan designs includes serially shifting input test data into the test access port controller and the test design logic under control of the system clock. Then the test access port controller is operated under control of the test clock for at least one cycle to generate resulting output test data. The resulting output test data is serially shifted out of the test access port controller and the test design logic under control of the system clock.

公开(公告)号：EP0792486B1

公开(公告)日：2000-04-12

申请号：EP95923926.0

申请日：1995-06-16

申请人： CRAY RESEARCH, INC.

发明人： WEST, Jeffrey, D.

IPC分类号： G06F11/267 ,  G01R31/28

CPC分类号： G01R31/318552

摘要： A test access port controller for use in a level sensitive scan design having test design logic including at least one serial scan test path. The test access port controller includes test access port controller logic operable in a system test mode for controlling the serial shifting of input test data into the at least one serial scan test path and for controlling serial shifting of resulting output test data out of the at least one serial scan test path after performance of system mode test under control of a test clock. The test access port controller further includes clock logic for providing the test clock to the test access port controller logic and the test design logic in system test mode. The clock logic further provides a system clock to the test access port controller logic and test design logic in a fabrication test mode to serially shift input test data into the test access port controller logic and test design logic and to serially shift resulting output data out of the test access port controller logic and test design logic after operation of the test access port controller logic and test design logic under one cycle of test clock. A test method for such level sensitive scan designs includes serially shifting input test data into the test access port controller and the test design logic under control of the system clock. Then the test access port controller is operated under control of the test clock for at least one cycle to generate resulting output test data. The resulting output test data is serially shifted out of the test access port controller and the test design logic under control of the system clock.