公开(公告)号：EP1192559A2

公开(公告)日：2002-04-03

申请号：EP00937633.6

申请日：2000-05-19

申请人： Cadence Design Systems, Inc.

发明人： GINETTI, Arnold

IPC分类号： G06F17/00

CPC分类号： G06F17/505 ,  G06F17/5072

摘要： A method for estimating the position of a matched cell takes into account the interconnective ties of that cell, without relying on the location of cells connected to the matched cell. The new method is referred to as the Weighted Center of Mass of Covered method. In this method, weights are given to the various nodes which are part of the match. These weights are based on the number of connections between the nodes and child nodes of the match. The placement of the matched cell is based on the initial positions given to the nodes making up the match, and the weights calculated for those nodes.

公开(公告)号：EP1192559B1

公开(公告)日：2003-10-01

申请号：EP00937633.6

申请日：2000-05-19

申请人： Cadence Design Systems, Inc.

发明人： GINETTI, Arnold

IPC分类号： G06F17/00

CPC分类号： G06F17/505 ,  G06F17/5072

摘要： A method for estimating the position of a matched cell takes into account the interconnective ties of that cell, without relying on the location of cells connected to the matched cell. The new method is referred to as the Weighted Center of Mass of Covered method. In this method, weights are given to the various nodes which are part of the match. These weights are based on the number of connections between the nodes and child nodes of the match. The placement of the matched cell is based on the initial positions given to the nodes making up the match, and the weights calculated for those nodes.

公开(公告)号：EP1330743A1

公开(公告)日：2003-07-30

申请号：EP01992956.1

申请日：2001-10-30

申请人： Cadence Design Systems, Inc.

发明人： GINETTI, Arnold

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F17/5072

摘要： A feasible floorplan of a circuit is determined and budgeted in the early phases of circuit design. The process of determining the floorplan and budget (FIGURE 1, step 3) includes estimating RTL complexity, physical partitioning, block placement, block i/o placement and top level global routing, and verifying feasibility of the floorplan (FIGURE 1, step 5). Allocation of global timing constraints to each block is performed by producing logic cones representing timing of circuit paths in each block. The circuit paths are optimized to determine a feasible timing for each block (FIGURE 1, step 8). The global constraints are allocated proportionally to each block based on the feasible timing for each block.