公开(公告)号：EP1145159A3

公开(公告)日：2002-07-10

申请号：EP99954722.7

申请日：1999-09-30

申请人： Cadence Design Systems, Inc.

发明人： CHANG, Henry ,  COOKE, Larry ,  HUNT, Merrill ,  KE, Wuudiann ,  LENNARD, Christopher, K. ,  MARTIN, Grant ,  PATERSON, Peter ,  TRUONG, Khoan ,  VENKATRAMANI, Kumar

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F17/5022 ,  G06F2217/66

公开(公告)号：EP1145159A2

公开(公告)日：2001-10-17

申请号：EP99954722.7

申请日：1999-09-30

申请人： Cadence Design Systems, Inc.

发明人： CHANG, Henry ,  COOKE, Larry ,  HUNT, Merrill ,  KE, Wuudiann ,  LENNARD, Christopher, K. ,  MARTIN, Grant ,  PATERSON, Peter ,  TRUONG, Khoan ,  VENKATRAMANI, Kumar

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F17/5022 ,  G06F2217/66

摘要： A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.

公开(公告)号：EP1299739B1

公开(公告)日：2004-08-11

申请号：EP01950619.5

申请日：2001-06-28

申请人： Cadence Design Systems, Inc.

发明人： COOKE, Laurence, H. ,  LENNARD, Christopher, K.

IPC分类号： G01R31/3183 ,  G01R31/3185 ,  G06F17/50

CPC分类号： G06F8/443 ,  G01R31/318342 ,  G06F17/5045 ,  G06F17/5068

摘要： A method of testing an integrated circuit including component blocks of random logic in a manufacturing environment is disclosed. The method includes the steps of performing built-in self tests, at least in part to test memory and data paths of the integrated circuit, performing diagnostics tests, at least in part to test the component blocks of random logic individually, performing stress tests using test vectors, at least in part to test the component blocks of random logic collectively; and performing scan-based tests of the integrated circuit, at least in part to test for structural faults in the integrated circuit.

公开(公告)号：EP1299739A2

公开(公告)日：2003-04-09

申请号：EP01950619.5

申请日：2001-06-28

申请人： Cadence Design Systems, Inc.

发明人： COOKE, Laurence, H. ,  LENNARD, Christopher, K.

IPC分类号： G01R31/3183 ,  G01R31/3185 ,  G06F17/50

CPC分类号： G06F8/443 ,  G01R31/318342 ,  G06F17/5045 ,  G06F17/5068

摘要： A method of testing an integrated circuit including component blocks of random logic in a manufacturing environment is disclosed. The method includes the steps of performing built-in self tests, at least in part to test memory and data paths of the integrated circuit, performing diagnostics tests, at least in part to test the component blocks of random logic individually, performing stress tests using test vectors, at least in part to test the component blocks of random logic collectively; and performing scan-based tests of the integrated circuit, at least in part to test for structural faults in the integrated circuit.