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1.发明公开Circuit for reassigning the power-on processor in a multiprocessing system 失效einch Mehrprozessorensystem的Schaltung zum Wiederzuweisen des Einschaltsprozessors
公开(公告)号：EP0720094A2
公开(公告)日：1996-07-03
申请号：EP95309547.8
申请日：1995-12-29
CPC分类号： G06F15/177 , G06F1/26 , G06F11/1417
摘要： A hot spare boot circuit that automatically switches from a non-operational CPU to an operational CPU for powering up the computer system. In the multiprocessor computer system, a first CPU is designated to perform power on operations. If the first CPU fails, which is determined when a dead man counter in the hot spare boot circuit times out, the hot spare circuit ensures that the first CPU is in a disabled state. Next, the hot spare boot circuit identifies an operational second CPU, reinitializing certain ID information as necessary such that the second CPU can properly perform power on operations. The hot spare boot then awakens the second CPU, using a startup interprocessor interrupt in one embodiment, or simply negating the hard reset of the second CPU in a second embodiment. The second CPU then proceeds to perform the power on functions.
摘要翻译： 一个热备用引导电路，可自动从非操作CPU切换到运行CPU，以便为计算机系统供电。 在多处理器计算机系统中，指定第一CPU执行上电操作。 如果第一个CPU出现故障，当热备用引导电路中的死亡计数器超时时，该热备用电路确保第一个CPU处于禁用状态。 接下来，热备用引导电路识别操作的第二CPU，根据需要重新初始化某些ID信息，使得第二CPU可以正常地执行上电操作。 在第二实施例中，热备用引导然后唤醒第二CPU，在一个实施例中使用启动处理器中断，或简单地否定第二CPU的硬复位。 然后第二个CPU继续执行上电功能。
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2.发明授权Circuit for reassigning the power-on processor in a multiprocessing system 失效电路的重新分配在多处理器系统中的Einschaltsprozessors
公开(公告)号：EP0720094B1
公开(公告)日：2002-07-24
申请号：EP95309547.8
申请日：1995-12-29
CPC分类号： G06F15/177 , G06F1/26 , G06F11/1417
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3.发明公开Circuit for reassigning the power-on processor in a multiprocessing system 失效电路的重新分配在多处理器系统中的Einschaltsprozessors
公开(公告)号：EP0720094A3
公开(公告)日：1997-04-23
申请号：EP95309547.8
申请日：1995-12-29
CPC分类号： G06F15/177 , G06F1/26 , G06F11/1417
摘要： A hot spare boot circuit that automatically switches from a non-operational CPU to an operational CPU for powering up the computer system. In the multiprocessor computer system, a first CPU is designated to perform power on operations. If the first CPU fails, which is determined when a dead man counter in the hot spare boot circuit times out, the hot spare circuit ensures that the first CPU is in a disabled state. Next, the hot spare boot circuit identifies an operational second CPU, reinitializing certain ID information as necessary such that the second CPU can properly perform power on operations. The hot spare boot then awakens the second CPU, using a startup interprocessor interrupt in one embodiment, or simply negating the hard reset of the second CPU in a second embodiment. The second CPU then proceeds to perform the power on functions.
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