公开(公告)号：EP0231595A3

公开(公告)日：1989-02-15

申请号：EP86308824.1

申请日：1986-11-12

申请人： DATA GENERAL CORPORATION

发明人： Wagner, Eric M. ,  Kiernicki, Martin ,  Freeman, John L.

IPC分类号： G06F13/12 ,  G06F13/18 ,  G06F3/06

CPC分类号： G06F3/0601 ,  G06F13/124 ,  G06F13/18 ,  G06F2003/0692

摘要： An input/output controller (39) is provided in a data processing system having a local memory bus (37), a main memory (35) coupled to this bus and a host central processing unit (33) also coupled to the bus. The input/output controller (39) interfaces a plurality of input/output devices to the local memory bus (37) and includes a plurality of input/output device controllers (41,43,45), each adapted to be connected to at least one input/output device. A single microprocessor (49) manages the operations of the input/output controller (39) and a single buffer memory (47) stores a program of instructions for the microprocessor and temporarily stores data passing to or from the input/output devices. A gate array (51) for interfaces the input/output device controllers (41,43,45) to the local memory bus (37).

公开(公告)号：EP0231595A2

公开(公告)日：1987-08-12

申请号：EP86308824.1

申请日：1986-11-12

申请人： DATA GENERAL CORPORATION

发明人： Wagner, Eric M. ,  Kiernicki, Martin ,  Freeman, John L.

IPC分类号： G06F13/12 ,  G06F13/18 ,  G06F3/06

CPC分类号： G06F3/0601 ,  G06F13/124 ,  G06F13/18 ,  G06F2003/0692

摘要： An input/output controller (39) is provided in a data processing system having a local memory bus (37), a main memory (35) coupled to this bus and a host central processing unit (33) also coupled to the bus. The input/output controller (39) interfaces a plurality of input/output devices to the local memory bus (37) and includes a plurality of input/output device controllers (41,43,45), each adapted to be connected to at least one input/output device. A single microprocessor (49) manages the operations of the input/output controller (39) and a single buffer memory (47) stores a program of instructions for the microprocessor and temporarily stores data passing to or from the input/output devices. A gate array (51) for interfaces the input/output device controllers (41,43,45) to the local memory bus (37).

摘要翻译： 输入/输出控制器（39）设置在具有本地存储器总线（37），耦合到该总线的主存储器（35）和还耦合到总线的主机中央处理单元（33）的数据处理系统中。 输入/输出控制器（39）将多个输入/输出设备连接到本地存储器总线（37），并且包括多个输入/输出设备控制器（41,43,45），每个输入/输出设备控制器适于至少连接 一个输入/输出设备。 单个微处理器（49）管理输入/输出控制器（39）的操作，并且单个缓冲存储器（47）存储用于微处理器的指令程序，并且临时存储传送到输入/输出设备或从输入/输出设备传送的数据。 一个用于将输入/输出设备控制器（41,43,45）连接到本地存储器总线（37）的门阵列（51）。