公开(公告)号：EP0206891A2

公开(公告)日：1986-12-30

申请号：EP86401214

申请日：1986-06-05

申请人： DIGITAL EQUIPMENT CORP

发明人： SMITH WILLIAM H ,  DOUCETTE RICHARD L

IPC分类号： H03K3/286 ,  H03K3/2885 ,  H03K19/086

CPC分类号： H03K19/0866 ,  H03K3/2885

摘要： A latch circuit including an input logic network that incorporates emitter-coupled logic switching arrangements connected in multiple levels to perform logical operations on the received input signals. The latch circuit is controlled by differential clock signals coupled to a differential switch circuit that is connected to the input logic network to form another switch level. An output buffer is connected to the input logic network to generate output signals of selected logic voltage levels. When the differential clock signals are in a pass condition, the input logic network is enabled to transmit an output signal to the output buffer. When the differential clock signals are in a latch, or hold, condition, the input logic network is disabled and a feedback network is enabled to maintain the signal to the output buffer in the conditions it was in when the differential clock signals changed conditions.

摘要翻译： 一种锁存电路，包括输入逻辑网络，该输入逻辑网络包含以多个级别连接的发射极耦合逻辑开关装置，以对所接收的输入信号执行逻辑运算。 锁存电路由耦合到差分开关电路的差分时钟信号控制，差分开关电路连接到输入逻辑网络以形成另一个开关电平。 输出缓冲器连接到输入逻辑网络以产生所选逻辑电压电平的输出信号。 当差分时钟信号处于通过状态时，输入逻辑网络使能将输出信号发送到输出缓冲器。 当差分时钟信号处于锁存或保持状态时，禁止输入逻辑网络，并且在差分时钟信号变化的条件下使反馈网络能够使信号保持在输出缓冲器中。