摘要:
A digital interface for PCM data, allowing bidirectional data exchange between a processing unit (120) and a PCM channel (17), the data being transmitted in records each divided into a plurality of groups (bytes) transmitted at successive periods in homologous time intervals. This interface comprises a reception memory (162) receiving from the PCM channel (17) groups to be stored, a control processor (120) connected to the reception memory and receiving therefrom complete data records, a transmission memory (163), receiving from the control processor data records to be transmitted on the PCM channel (17). The reception and transmission memories (162,163) are divided into a plurality of buffers storing data records received or to be transmitted in present time intervals. A timing phase sequencer (164) is connected to the memories (162,163) and to a protocol controller (165) for detecting a data record reception beginning and correctly storing data groups of a same record in the reception memory and controlling transmission of a data record in data groups from the transmission memory towards the PCM channel in preset time intervals.
摘要:
A system for automatic control of devices, apparata and peripheral units for signal switching and processing, comprising a single central control unit (2) for controlling a plurality of terminals (4) and at least one internal digital line (3) interposed between the central control unit and the terminals and defining a time sharing transmissive channel, divided into a plurality of time slots, with each terminal (4) being fixedly associated to at least one preset time intervals.
摘要:
A digital interface for PCM data, allowing bidirectional data exchange between a processing unit (120) and a PCM channel (17), the data being transmitted in records each divided into a plurality of groups (bytes) transmitted at successive periods in homologous time intervals. This interface comprises a reception memory (162) receiving from the PCM channel (17) groups to be stored, a control processor (120) connected to the reception memory and receiving therefrom complete data records, a transmission memory (163), receiving from the control processor data records to be transmitted on the PCM channel (17). The reception and transmission memories (162,163) are divided into a plurality of buffers storing data records received or to be transmitted in present time intervals. A timing phase sequencer (164) is connected to the memories (162,163) and to a protocol controller (165) for detecting a data record reception beginning and correctly storing data groups of a same record in the reception memory and controlling transmission of a data record in data groups from the transmission memory towards the PCM channel in preset time intervals.
摘要:
A system for automatic control of devices, apparata and peripheral units for signal switching and processing, comprising a single central control unit (2) for controlling a plurality of terminals (4) and at least one internal digital line (3) interposed between the central control unit and the terminals and defining a time sharing transmissive channel, divided into a plurality of time slots, with each terminal (4) being fixedly associated to at least one preset time intervals.