公开(公告)号：EP4339923A1

公开(公告)日：2024-03-20

申请号：EP23197074.0

申请日：2023-09-13

申请人： Electronics and Telecommunications Research Institute

发明人： PARK, Seong-Cheon ,  NA, Jung-Chan ,  KIM, Hyunwoo ,  JANG, Suyeon

IPC分类号： G09C1/00 ,  H04L9/00 ,  G06F7/50 ,  G06F7/523 ,  G06F7/72

摘要： Disclosed is an accelerator which includes a first to a K-th stage performing an NTT (Number Theoretic Transform) operation of first input data including a polynomial of a homomorphic ciphertext, the first to K-th stages being connected in series, and a first assist circuit generating a first to a K-th enable signal based on a degree of the polynomial of the first input data. Each of the first to K-th stages performs a butterfly operation of the first input data or corresponding output data of a previous stage in response to that the corresponding enable signal among the first to K-th enable signals indicates a first logical value, and bypasses the first input data or the corresponding output data of the previous stage in response to that the corresponding enable signal among the first to K-th enable signals indicates a second logical value.