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1.发明公开Dynamic instruction set augmentation and multiprocessor synchronization using electronically reconfigurable logic arrays 审中-公开并行编译，仿真和计算机程序和硬件模型设计Kompilerorientiertes设备
公开(公告)号：EP1501009A1
公开(公告)日：2005-01-26
申请号：EP04014944.5
申请日：1998-10-21
申请人： FTL Systems Inc.
CPC分类号： G06F9/3877 , G06F8/10 , G06F8/30 , G06F9/3897 , G06F15/7867 , G06F17/5009 , G06F17/5027 , G06F2217/86
摘要： An apparatus is disclosed for integrating a general purpose processor with one or more electronically reconfigurable logic arrays so that a subset of the general purpose processor instruction set encodings (opcodes) may control functionality implemented by a reconfigurable logic block analogous to operations implemented by fixed functionality execution units conventionally incorporated within a processor.
摘要翻译： 一种装置，光盘游离缺失为INTEGRA婷通用处理器与一个或多个电子可重新配置逻辑阵列所以没有通用处理器指令集编码的子集（操作码）可以控制在由可重构逻辑块类似于由上执行的固定功能实现的操作所实现的功能 单元的处理器内常规地并入本文。
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2.发明公开Dynamic instruction set augmentation and multiprocessor synchronization using electronically reconfigurable logic arrays 审中-公开并行编译，仿真和计算机程序和硬件模型设计Kompilerorientiertes设备
公开(公告)号：EP2328082A3
公开(公告)日：2011-12-14
申请号：EP10182661.8
申请日：1998-10-21
申请人： FTL Systems Inc.
CPC分类号： G06F9/3877 , G06F8/10 , G06F8/30 , G06F9/3897 , G06F15/7867 , G06F17/5009 , G06F17/5027 , G06F2217/86
摘要： An apparatus is disclosed for integrating a general purpose processor with one or more electronically reconfigurable logic arrays so that a subset of the general purpose processor instruction set encodings (opcodes) may control functionality implemented by a reconfigurable logic block analogous to operations implemented by fixed functionality execution units conventionally incorporated within a processor.
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3.发明公开Dynamic instruction set augmentation and multiprocessor synchronization using electronically reconfigurable logic arrays 审中-公开并行编译，仿真和计算机程序和硬件模型设计Kompilerorientiertes设备
公开(公告)号：EP2328082A2
公开(公告)日：2011-06-01
申请号：EP10182661.8
申请日：1998-10-21
申请人： FTL Systems Inc.
CPC分类号： G06F9/3877 , G06F8/10 , G06F8/30 , G06F9/3897 , G06F15/7867 , G06F17/5009 , G06F17/5027 , G06F2217/86
摘要： An apparatus is disclosed for integrating a general purpose processor with one or more electronically reconfigurable logic arrays so that a subset of the general purpose processor instruction set encodings (opcodes) may control functionality implemented by a reconfigurable logic block analogous to operations implemented by fixed functionality execution units conventionally incorporated within a processor.
摘要翻译： 一种装置，光盘游离缺失为INTEGRA婷通用处理器与一个或多个电子可重新配置逻辑阵列所以没有通用处理器指令集编码的子集（操作码）可以控制在由可重构逻辑块类似于由上执行的固定功能实现的操作所实现的功能 单元的处理器内常规地并入本文。
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