公开(公告)号：EP0367221A2

公开(公告)日：1990-05-09

申请号：EP89120187.3

申请日：1989-10-31

申请人： FUJITSU LIMITED

发明人： Ishikawa, Minoru ,  Nakata, Nobuki

IPC分类号： H04J3/08

CPC分类号： H04J3/08

摘要： An improved drop/insert multiplexer for use in a channel access unit allowed to use channel slots in common for data channels in directions 1 and 2 and decreased in wiring between a MULDEM section and a CH section thereof by adopting a time division multiplex transmission system for transmitting receive and send channel pulses. The drop/insert multiplexer comprises, at the receive side thereof, a time slot phase difference setting stage (21) for providing a predetermined phase difference between received timing signals as well as received data from the direction 1 and 2, a receive channel pulse generat­ing stage (22) for generating multiplexed channels pulses, a receive channel pulse decoding stage (31) and a decoder (33) for reproducing a voice signal by receiving selected received data and, at the send side thereof, a time slot phase difference correcting stage (23) to correct the set phase difference for sending out channel data to the direction 1 or 2, a send channel pulse generating stage (24) for generating multiplexed channel pulses, a send chan­nel pulse decoding stage (34) and a coder (36) for producing PCM signals to send out to the direction 1 or 2 as channel data.

摘要翻译： 一种用于信道接入单元的改进的丢弃/插入多路复用器允许在方向1和2上的数据信道共同使用信道时隙，并且通过采用时分多路复用传输系统，在MULDEM部分和其CH部分之间的布线中减少 发送接收和发送信道脉冲。 插入/插入复用器在其接收侧包括用于在接收到的定时信号之间提供预定相位差的时隙相位差设置级（21）以及来自方向1和2的接收数据，产生接收信道脉冲 用于产生多路复用信道脉冲的级（22），接收信道脉冲解码级（31）和用于通过接收所选接收数据再现语音信号的解码器（33），并且在其发送侧具有时隙相位差校正级 （23），用于校正用于向方向1或2发送信道数据的设定相位差，用于产生多路复用信道脉冲的发送信道脉冲产生级（24），发送信道脉冲解码级（34）和编码器（36） ），用于产生PCM信号作为通道数据发送到方向1或2。

公开(公告)号：EP0367221A3

公开(公告)日：1992-05-20

申请号：EP89120187.3

申请日：1989-10-31

申请人： FUJITSU LIMITED

发明人： Ishikawa, Minoru ,  Nakata, Nobuki

IPC分类号： H04J3/08

CPC分类号： H04J3/08

摘要： An improved drop/insert multiplexer for use in a channel access unit allowed to use channel slots in common for data channels in directions 1 and 2 and decreased in wiring between a MULDEM section and a CH section thereof by adopting a time division multiplex transmission system for transmitting receive and send channel pulses. The drop/insert multiplexer comprises, at the receive side thereof, a time slot phase difference setting stage (21) for providing a predetermined phase difference between received timing signals as well as received data from the direction 1 and 2, a receive channel pulse generat­ing stage (22) for generating multiplexed channels pulses, a receive channel pulse decoding stage (31) and a decoder (33) for reproducing a voice signal by receiving selected received data and, at the send side thereof, a time slot phase difference correcting stage (23) to correct the set phase difference for sending out channel data to the direction 1 or 2, a send channel pulse generating stage (24) for generating multiplexed channel pulses, a send chan­nel pulse decoding stage (34) and a coder (36) for producing PCM signals to send out to the direction 1 or 2 as channel data.

公开(公告)号：EP0367221B1

公开(公告)日：1995-04-12

申请号：EP89120187.3

申请日：1989-10-31

申请人： FUJITSU LIMITED

发明人： Ishikawa, Minoru ,  Nakata, Nobuki

IPC分类号： H04J3/08

CPC分类号： H04J3/08

公开(公告)号：EP0393514A2

公开(公告)日：1990-10-24

申请号：EP90107034.2

申请日：1990-04-12

申请人： FUJITSU LIMITED

发明人： Ishikawa, Minoru ,  Nakata, Nobuki

IPC分类号： H04J3/12 ,  H04J3/06

CPC分类号： H04J3/062 ,  Y10S370/914

摘要： A channel access system comprises n channel parts (21₁-21 n ) for receiving m channels of voice signals and for outputting voice frequency data and signaling data, and a multiplexer part (22) for receiving the voice frequency data and the signaling data of the m channels from the n channel parts and for supplying channel access signals to the n channel parts for designating a channel of the voice frequency data, where each of the n channel parts include a coder (23) for coding a corresponding one of the voice signals into one of the voice frequency data, a decoder (25) for decoding the channel access signals and for generating a synchronizing signal (SYNC1) which is synchronized to a corresponding one of the channel access signals which designates its own channel, a signaling converter (24) for converting the corresponding one of the signaling signals into a corresponding one of the signaling data, and a speed converting circuit (26) for converting a transmission speed of the signaling data from a first transmission speed to a second transmission speed which is higher than the first transmission speed. The synchronizing signal (SYNC1) controls a coding timing of the coder and a speed conversion timing of the speed converting circuit.

摘要翻译： 信道接入系统包括：n个信道部分（211-21n），用于接收m个话音信号，并输出语音频率数据和信令数据;以及多路复用器部分（22），用于接收语音频率数据和m个信令数据 用于向n个信道部分提供信道接入信号以指定语音频率数据的信道，其中n个信道部分中的每一个包括编码器（23），用于将对应的一个语音信号编码成 语音频率数据中的一个，用于解码信道接入信号并用于产生与指定其自己的信道的信道接入信号中的相应一个同步的同步信号（SYNC1）的解码器（25）;信令转换器 ），用于将所述信令信号中的相应一个信号转换成所述信令数据中的相应一个;以及速度转换电路（26），用于转换信令d的传输速度 从第一传输速度到高于第一传输速度的第二传输速度。 同步信号（SYNC1）控制编码器的编码定时和速度转换电路的速度转换定时。

公开(公告)号：EP0393514B1

公开(公告)日：1996-07-17

申请号：EP90107034.2

申请日：1990-04-12

申请人： FUJITSU LIMITED

发明人： Ishikawa, Minoru ,  Nakata, Nobuki

IPC分类号： H04J3/12 ,  H04J3/06

CPC分类号： H04J3/062 ,  Y10S370/914

公开(公告)号：EP0393514A3

公开(公告)日：1992-09-23

申请号：EP90107034.2

申请日：1990-04-12

申请人： FUJITSU LIMITED

发明人： Ishikawa, Minoru ,  Nakata, Nobuki

IPC分类号： H04J3/12 ,  H04J3/06

CPC分类号： H04J3/062 ,  Y10S370/914

摘要： A channel access system comprises n channel parts (21₁-21 n ) for receiving m channels of voice signals and for outputting voice frequency data and signaling data, and a multiplexer part (22) for receiving the voice frequency data and the signaling data of the m channels from the n channel parts and for supplying channel access signals to the n channel parts for designating a channel of the voice frequency data, where each of the n channel parts include a coder (23) for coding a corresponding one of the voice signals into one of the voice frequency data, a decoder (25) for decoding the channel access signals and for generating a synchronizing signal (SYNC1) which is synchronized to a corresponding one of the channel access signals which designates its own channel, a signaling converter (24) for converting the corresponding one of the signaling signals into a corresponding one of the signaling data, and a speed converting circuit (26) for converting a transmission speed of the signaling data from a first transmission speed to a second transmission speed which is higher than the first transmission speed. The synchronizing signal (SYNC1) controls a coding timing of the coder and a speed conversion timing of the speed converting circuit.