公开(公告)号：EP1624635A2

公开(公告)日：2006-02-08

申请号：EP04257726.2

申请日：2004-12-13

申请人： FUJITSU LIMITED

发明人： Kato, Shinya, c/o Fujitsu Limited ,  Nisiyama, Ryuichi, c/o Fujitsu Limited ,  Takahashi, Jin, c/o Fujitsu Limited ,  Kyono, Takayoshi, c/o Fujitsu Microelectronics

IPC分类号： H04L25/14

CPC分类号： H04L7/0331 ,  G06F13/4273 ,  H04L7/005 ,  H04L25/14

摘要： A data transmitter and a data receiver generate respective synchronous signals from a common reference signal. The data receiver adjusts a phase of a first clock signal using each one of one-bit data signals each consisting of a single bit of received parallel data, so that a setup time and a hold time are ensured for the each one-bit data signal, and loads each one-bit data signal into a data buffer in accordance with the adjusted clock signal. Then, the data receiver reads the data held in the data buffer, in accordance with a second clock signal and in synchronization with the receiver synchronous signal. A memory position where the data signal is to be loaded is initialized when a training pattern transmitted in synchronization with the transmitter synchronous signal is detected.

摘要翻译： 一种数据发送器和数据接收器产生从公共参考信号respectivement同步信号。 数据接收机bestimmt使用一比特之一的每个数据信号接收的并行数据的单位的每个由第一时钟信号的相位，所以没建立时间和保持时间是有保证的用于每一个比特的数据信号 和负载的每一个一比特数据信号与调整的时钟信号在雅舞蹈数据缓冲器。 然后，数据接收器读取该数据缓冲器中保持的数据，与第二时钟信号雅舞蹈，并与接收机的同步信号同步。 其中所述数据信号是要被加载的存储器中的位置被初始化。当锻炼图案反式被检测到发射机同步信号同步mitted。

公开(公告)号：EP1624635B1

公开(公告)日：2014-09-24

申请号：EP04257726.2

申请日：2004-12-13

申请人： FUJITSU LIMITED

发明人： Kato, Shinya, c/o Fujitsu Limited ,  Nisiyama, Ryuichi, c/o Fujitsu Limited ,  Takahashi, Jin, c/o Fujitsu Limited ,  Kyono, Takayoshi, c/o Fujitsu Microelectronics

IPC分类号： H04L25/14 ,  G06F13/42 ,  H04L7/033

CPC分类号： H04L7/0331 ,  G06F13/4273 ,  H04L7/005 ,  H04L25/14

公开(公告)号：EP1624635A3

公开(公告)日：2012-07-11

申请号：EP04257726.2

申请日：2004-12-13

申请人： FUJITSU LIMITED

发明人： Kato, Shinya, c/o Fujitsu Limited ,  Nisiyama, Ryuichi, c/o Fujitsu Limited ,  Takahashi, Jin, c/o Fujitsu Limited ,  Kyono, Takayoshi, c/o Fujitsu Microelectronics

IPC分类号： H04L25/14 ,  G06F13/42 ,  H04L7/033

CPC分类号： H04L7/0331 ,  G06F13/4273 ,  H04L7/005 ,  H04L25/14

摘要： A data transmitter and a data receiver generate respective synchronous signals from a common reference signal. The data receiver adjusts a phase of a first clock signal using each one of one-bit data signals each consisting of a single bit of received parallel data, so that a setup time and a hold time are ensured for the each one-bit data signal, and loads each one-bit data signal into a data buffer in accordance with the adjusted clock signal. Then, the data receiver reads the data held in the data buffer, in accordance with a second clock signal and in synchronization with the receiver synchronous signal. A memory position where the data signal is to be loaded is initialized when a training pattern transmitted in synchronization with the transmitter synchronous signal is detected.